ZHCSJ47E March 2017 – December 2018 DRA76P , DRA77P
ADVANCE INFORMATION for pre-production products; subject to change without notice.
| PARAMETER | MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| Signal Names in MUXMODE 0: i2c1_sda, i2c1_scl, i2c2_sda, i2c2_scl; | ||||||
| Balls: C20 / C19 / C24 / F15 | ||||||
| I2C Standard Mode – 1.8 V | ||||||
| VIH | Input high-level threshold | 0.7 × VDDS(1) | V | |||
| VIL | Input low-level threshold | 0.3 × VDDS(1) | V | |||
| Vhys | Hysteresis | 0.1 × VDDS(1) | V | |||
| IIN | Input current at each I/O pin with an input voltage between 0.1 × VDDS to 0.9 × VDDS | 12 | µA | |||
| IOZ | IOZ(IPAD Current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the Rx + weak pullup/pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ | 12 | µA | |||
| CIN | Input capacitance | 10 | pF | |||
| VOL3 | Output low-level threshold open-drain at 3-mA sink current | 0.2 × VDDS(1) | V | |||
| IOLmin | Low-level output current @VOL = 0.2 × VDDS | 3 | mA | |||
| tOF | Output fall time from VIHmin to VILmax with a bus capacitance CB from 5 pF to 400 pF | 250 | ns | |||
| I2C Fast Mode – 1.8 V | ||||||
| VIH | Input high-level threshold | 0.7 × VDDS(1) | V | |||
| VIL | Input low-level threshold | 0.3 × VDDS(1) | V | |||
| Vhys | Hysteresis | 0.1 × VDDS(1) | V | |||
| IIN | Input current at each I/O pin with an input voltage between 0.1 × VDDS to 0.9 × VDDS | 12 | µA | |||
| IOZ | IOZ(IPAD Current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the Rx + weak pullup/pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ | 12 | µA | |||
| CIN | Input capacitance | 10 | pF | |||
| VOL3 | Output low-level threshold open-drain at 3-mA sink current | 0.2 × VDDS(1) | V | |||
| IOLmin | Low-level output current @VOL = 0.2 × VDDS | 3 | mA | |||
| tOF | Output fall time from VIHmin to VILmax with a bus capacitance CB from 10 pF to 400 pF | 20 + 0.1 × CB | 250 | ns | ||
| I2C Standard Mode – 3.3 V | ||||||
| VIH | Input high-level threshold | 0.7 × VDDS(1) | V | |||
| VIL | Input low-level threshold | 0.3 × VDDS(1) | V | |||
| Vhys | Hysteresis | 0.05 × VDDS(1) | V | |||
| IIN | Input current at each I/O pin with an input voltage between 0.1 × VDDS to 0.9 × VDDS | 31 | 80 | µA | ||
| IOZ | IOZ(IPAD Current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the Rx + weak pullup/pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ | 31 | 80 | µA | ||
| CIN | Input capacitance | 10 | pF | |||
| VOL3 | Output low-level threshold open-drain at 3-mA sink current | 0.4 | V | |||
| IOLmin | Low-level output current @VOL = 0.4 V | 3 | mA | |||
| IOLmin | Low-level output current @VOL = 0.6 V for full drive load (400 pF/400 kHz) | 6 | mA | |||
| tOF | Output fall time from VIHmin to VILmax with a bus capacitance CB from 5 pF to 400 pF | 250 | ns | |||
| I2C Fast Mode – 3.3 V | ||||||
| VIH | Input high-level threshold | 0.7 × VDDS(1) | V | |||
| VIL | Input low-level threshold | 0.3 × VDDS(1) | V | |||
| Vhys | Hysteresis | 0.05 × VDDS(1) | V | |||
| IIN | Input current at each I/O pin with an input voltage between 0.1 × VDDS to 0.9 × VDDSS | 31 | 80 | µA | ||
| IOZ | IOZ(IPAD Current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the Rx + weak pullup/pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ | 31 | 80 | µA | ||
| CIN | Input capacitance | 10 | pF | |||
| VOL3 | Output low-level threshold open-drain at 3-mA sink current | 0.4 | V | |||
| IOLmin | Low-level output current @VOL = 0.4 V | 3 | mA | |||
| IOLmin | Low-level output current @VOL = 0.6 V for full drive load (400pF/400kHz) | 6 | mA | |||
| tOF | Output fall time from VIHmin to VILmax with a bus capacitance CB from 10 pF to 200 pF (Proper External Resistor Value should be used as per I2C spec) | 20 + 0.1 × CB | 250 | ns | ||
| Output fall time from VIHmin to VILmax with a bus capacitance CB from 300 pF to 400 pF (Proper External Resistor Value should be used as per I2C spec) | 40 | 290 | ||||