ZHCSJ47E March 2017 – December 2018 DRA76P , DRA77P
ADVANCE INFORMATION for pre-production products; subject to change without notice.
Table 5-134 and Table 5-135 present timing requirements and switching characteristics for MMC1 - SDR50 in receiver and transmitter mode (see Figure 5-86 and Figure 5-87).
| NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
|---|---|---|---|---|---|---|
| SDR503 | tsu(cmdV-clkH) | Setup time, mmc1_cmd valid before mmc1_clk rising clock edge | 1.48 | ns | ||
| SDR504 | th(clkH-cmdV) | Hold time, mmc1_cmd valid after mmc1_clk rising clock edge | 1.6 | ns | ||
| SDR507 | tsu(dV-clkH) | Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge | 1.48 | ns | ||
| SDR508 | th(clkH-dV) | Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge | 1.6 | ns |
| NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
|---|---|---|---|---|---|
| SDR501 | fop(clk) | Operating frequency, mmc1_clk | 96 | MHz | |
| SDR502H | tw(clkH) | Pulse duration, mmc1_clk high | 0.5P-0.185 (1) | ns | |
| SDR502L | tw(clkL) | Pulse duration, mmc1_clk low | 0.5P-0.185 (1) | ns | |
| SDR505 | td(clkL-cmdV) | Delay time, mmc1_clk falling clock edge to mmc1_cmd transition | -3.66 | 1.46 | ns |
| SDR506 | td(clkL-dV) | Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition | -3.66 | 1.46 | ns |
Figure 5-86 MMC/SD/SDIO in - High-Speed SDR50 - Receiver Mode
Figure 5-87 MMC/SD/SDIO in - High-Speed SDR50 - Transmitter Mode