ZHCSJ47E March 2017 – December 2018 DRA76P , DRA77P
ADVANCE INFORMATION for pre-production products; subject to change without notice.
Table 7-23 shows the stackup and feature sizes required for these types of PCIe connections.
| PARAMETER | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|
| Number of ground plane cuts allowed within PCIe routing region | - | - | 0 | Cuts |
| Number of layers between PCIe routing area and reference plane (1) | - | - | 0 | Layers |
| PCB Routing clearance | 4 | Mils | ||
| PCB Trace width | 4 | Mils |