ZHCSJ47E March 2017 – December 2018 DRA76P , DRA77P
ADVANCE INFORMATION for pre-production products; subject to change without notice.
The minimum stackup required for routing the Device is a six-layer stackup as shown in Table 7-32. Additional layers may be added to the PCB stackup to accommodate other circuitry or to reduce the size of the PCB footprint.
| LAYER | TYPE | DESCRIPTION |
|---|---|---|
| 1 | Signal | Top routing mostly horizontal |
| 2 | Plane | Ground |
| 3 | Plane | Power |
| 4 | Signal | Internal routing |
| 5 | Plane | Ground |
| 6 | Signal | Bottom routing mostly vertical |
Complete stackup specifications are provided in Table 7-33.
| NO. | PARAMETER | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| PS21 | PCB routing/plane layers | 6 | |||
| PS22 | Signal routing layers | 3 | |||
| PS23 | Full ground reference layers under DDR2 routing region(1) | 1 | |||
| PS24 | Full vdds_ddrx power reference layers under the DDR2 routing region(1) | 1 | |||
| PS25 | Number of reference plane cuts allowed within DDR routing region(2) | 0 | |||
| PS26 | Number of layers between DDR2 routing layer and reference plane(3) | 0 | |||
| PS27 | PCB routing feature size | 4 | Mils | ||
| PS28 | PCB trace width, w | 4 | Mils | ||
| PS29 | Single-ended impedance, Zo | 50 | 75 | Ω | |
| PS210 | Impedance control(5) | Z - 5 | Z | Z + 5 | Ω |