ZHCSJ47E March 2017 – December 2018 DRA76P , DRA77P
ADVANCE INFORMATION for pre-production products; subject to change without notice.
CAUTION
The I/O timings provided in Section 5.10, Timing Requirements and Switching Characteristics are valid only if signals within a single IOSET are used. The IOSETs are defined in the Table 5-177.
NOTE
For more information, see the On-Chip Debug Support / Debug Interfaces section of the Device TRM.
| SIGNAL NAME | DESCRIPTION | TYPE | BALL |
|---|---|---|---|
| emu0 | Emulator pin 0 | IO | F19 |
| emu1 | Emulator pin 1 | IO | C23 |
| emu2 | Emulator pin 2 | O | D9 |
| emu3 | Emulator pin 3 | O | D6 |
| emu4 | Emulator pin 4 | O | A6 |
| emu5 | Emulator pin 5 | O | C6, F1 |
| emu6 | Emulator pin 6 | O | E9, G2 |
| emu7 | Emulator pin 7 | O | D5, F8 |
| emu8 | Emulator pin 8 | O | F7, G1 |
| emu9 | Emulator pin 9 | O | E5, E7 |
| emu10 | Emulator pin 10 | O | D7, F2 |
| emu11 | Emulator pin 11 | O | A5, E3 |
| emu12 | Emulator pin 12 | O | B6, E1 |
| emu13 | Emulator pin 13 | O | C8, E2 |
| emu14 | Emulator pin 14 | O | C7, D2 |
| emu15 | Emulator pin 15 | O | A7, F3 |
| emu16 | Emulator pin 16 | O | C9, D1 |
| emu17 | Emulator pin 17 | O | A8, E4 |
| emu18 | Emulator pin 18 | O | B9, G3 |
| emu19 | Emulator pin 19 | O | A9, C5 |
| rtck | JTAG return clock | O | E18 |
| tclk | JTAG test clock | I | E20 |
| tdi | JTAG test data | I | B22 |
| tdo | JTAG test port data | O | C18 |
| tms | JTAG test port mode select. An external pull-up resistor should be used on this ball. | IO | F16 |
| trstn | JTAG test reset | I | D20 |