ZHCSJ47E March 2017 – December 2018 DRA76P , DRA77P
ADVANCE INFORMATION for pre-production products; subject to change without notice.
Table 7-37 lists the clock net classes for the DDR2 interface. Table 7-38 lists the signal net classes, and associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the termination and routing rules that follow.
| CLOCK NET CLASS | PIN NAMES |
|---|---|
| CK | ddrx_ck / ddrx_nck |
| DQS0 | ddrx_dqs0 / ddrx_dqsn0 |
| DQS1 | ddrx_dqs1 / ddrx_dqsn1 |
| DQS2(1) | ddrx_dqs2 / ddrx_dqsn2 |
| DQS3(1) | ddrx_dqs3 / ddrx_dqsn3 |
| SIGNAL NET CLASS | ASSOCIATED CLOCK
NET CLASS |
PIN NAMES |
|---|---|---|
| ADDR_CTRL | CK | ddrx_ba[2:0], ddrx_a[14:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen, ddrx_cke, ddrx_odti |
| DQ0 | DQS0 | ddrx_d[7:0], ddrx_dqm0 |
| DQ1 | DQS1 | ddrx_d[15:8], ddrx_dqm1 |
| DQ2(1) | DQS2 | ddrx_d[23:16], ddrx_dqm2 |
| DQ3(1) | DQS3 | ddrx_d[31:24], ddrx_dqm3 |