ZHCSG17B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
PLL2 has four input modes which can be selected by the user. These modes give more flexibility to adjust the PLL2 bandwidth. See Table 16.
| INPUT MODE | DESCRIPTION |
|---|---|
| Doubler Mode | The Input clock gets multiplied by 2. The duty cycle of the clock is <50%. |
| Doubler invert mode | This mode is same like the doubler mode, where the input clock gets multiplied by 2, but the duty cycle of the output clock is >50%. |
| Pulse mode | The duty cycle of the input clock is adjusted to a fixed value and is >50%. |
| RDIV mode | The input divider is used to divide down the frequency with the range as shown in Table 15. |