ZHCSG17B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
The PLL2_CTRL1 Register provides control of PLL2 features. Return to Register Map.
| BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| [7] | PLL2_EN_PULSE_GEN | RW | 0 | Enable Pulse Generator in PLL2 R input block. |
| [6] | PLL2_RDIV_BYP | RW | 0 | PLL2 R-Divider Bypass. When PLL2_RDIV_BYP is 1 the R-Divider is by-passed. |
| [5] | PLL2_DBL_EN_INV | RW | 0 | PLL2 Doubler Enable Invert. When PLL2_DBL_EN_INV is 1 the output of the PLL2 Doubler is inverted. |
| [4] | PLL2_PD_VARBIAS | RW | 0 | VCO Varactor Biasing PD. |
| [3] | PLL2_SMART_TRIM | RW | 1 | PLL2 Smart trim enable. If PLL2_SMART_TRIM is set to 1 then the initial calibration threshold is set by PLL2_AC_STRT_THRESHOLD and the final threshold is set by PLL2_AC_THRESHOLD. If PLL2_SMART_TRIM is 0 the threshold is set by PLL2_AC_THRESHOLD at all times. |
| [2] | PLL2_LCKDET_LOS_MASK | RW | 1 | PLL2 Lock Detect LOS Mask. When PLL2_LCKDET_LOS_MASK is 1 then Loss of Source has no effect on the PLL2 Lock Detect circuit. |
| [1] | PLL2_RDIV_DBL_EN | RW | 0 | PLL2 R-Divider Doubler Enable. |
| [0] | PLL2_PD_LD | RW | 1 | PLL2 Window Comparator Powerdown. |