4 修訂歷史記錄
Changes from A Revision (June 2017) to B Revision
- 刪除了雙環(huán)路 PLL 架構(gòu) 特性要點下的項目列表Go
- 添加了超低噪聲 特性要點Go
- 將 VCO 頻率單位從“5.8GHz 至 6.175GHz”更改為“5870MHz 至 6175MHz”Go
- Added LMK04616 device configuration informationGo
- Changed VCO frequency from: 5800 MHz to: 5870 MHzGo
- Added PACKAGE column to device configuration information tableGo
- Added LMK04616 row to device configuration information tableGo
- Added Footnote and link to LMK04616 datasheet Go
- Added OSCout polarity information to the OSCout/OSCout* pin descriptionGo
- Changed PLL1 phase detector maximum frequency from 40 MHz to 4 MHz Go
- Changed VCO tuning range minimum from: 5800 to: 5870Go
- Changed VOD symbol to VOD,pp to match mVpp units.Go
- Changed VOD symbol to VOD,pp to match mVpp units. Go
- Added content to the HSDS 4/6/8mA section Go
- Added content to the HCSL section Go
- Changed the VCXO Buffered Output section Go
- Changed VCO frequency to 5870 MHz to 6175 MHz and updated max output frequency to 2058 MHz Go
- Added content to the Programmable Output Formats section Go
- Changed HSDS to LVPECL With Bias Voltage Vb graphic captionGo
- Changed HCSL to LVPECL graphicGo
- Changed HSDS to LVPECL With Bias Voltage Vb graphic captionGo
- Changed HSDS to LVPECL graphicGo
- Added content to the OSCout section Go
- Added OSCin to OSCout differential results in clock inversion from OSCin to OSCout. Go
- Added Note to use TICS Pro EVM tool to calculate SDPLL loop filter values.Go
- Changed PLL1_PROP max from 255 to 127. Go
- Added PLL1_PROP_FL to table. Go
- Changed PLL1_FBCLK_INV and CLKinx_PLL1_INV for Low Pulse modeGo
- Changed PLL1_FBCLK_INV and CLKinx_PLL1_INV for High Pulse mode Go
- Deleted Examples of PLL1 SettingGo
- Changed the tuning range of the oscillator from: 5800 MHz to: 5870 MHzGo
- Added PLL2 DLD programming information and updated the PLLx DLD flowchart graphic Go
- Changed PLL1_STORAGE_CELL description from 40-bit thermometer code to 6-bit decimal value Go
- Clarified CTRL_VCXO represented as PLL1_STORAGE_CELL value Go
- Changed section from: Low Skew Mode to: Zero Delay Mode (ZDM) Go
- Changed Set Prop/Store-CP from "fast lock" value to "non-fast lock" value at end of flowchartGo
- Deleted references to tunable crystal Go
- Deleted reference to CLKin2 and CLKin3 Go
- Deleted use of external VCO for PLL2.Go
- Added register 0x85, 0x86, 0xF6, and 0xAD for PLL2 DLD to recommended programming sequenceGo
- Changed PLL1_PROP from 8 bit to 7 bit field in register map Go
- Changed PLL1_PROP_FL from 8 bit to 7 bit field in register map Go
- Changed PLL1_STORAGE_CELL 40 bit to 6 bit field. Not a 40 bit thermometer code. Set registers 0x66, 0x67, 0x68, 0x69 to RSRVD in register map Go
- Changed PLL2_PROP from 8 bit to 6 bit field in register map Go
- Changed PLL2_INTG from 8 bit to 5 bit field in register map Go
- Added register 0xAC for field PLL1_TSTMODE_REF_FB_EN in register mapGo
- Added register 0xAD for fields RESET_PLL2_DLD, PLL2_TSTMODE_REF_FB_EN, and PD_VCO_LDO in register mapGo
- Added register 0xF6 for PLL2_DLD_EN in register mapGo
- Deleted unused DEVID valuesGo
- Changed reset value for CHIPID from 0x1 to 0x3Go
- Changed reset value for CHIPVER from 0x1 to 0x1B Go
- Changed PLL1_PROP from 8 bit to 7 bit field in register definition Go
- Changed PLL1_PROP_FL from 8 bit to 7 bit field in register definition Go
- Deleted 'PLL1 Start-up in Holdover.' text from the PLL1_STARTUP_HOLDOVER_EN bit descriptionGo
- Changed PLL2_PROP field size from 8 bits to 6 bits in register definition Go
- Changed PLL2_INTG field from 8 bit to 5 bit field in register 0x80 definitionGo
- Added definition and requirement for setting PLL2_LD_WNDW_SIZE = 0 in register 0x85 definition Go
- Added definition and requirement for setting PLL2_LD_WNDW_SIZE_INITIAL = 0 in register 0x86 definitionGo
- Added note for using PLL1/2 REF/FB(SYS) status output for STAT0 Go
- Added note for using PLL1/2 REF/FB(SYS) status output for STAT1 Go
- Added note for using PLL1/2 REF/FB(SYS) status output for SYNC Go
- Added register 0xAC to register description. New field PLL1_TSTMODE_REF_FB_EN.Go
- Added register 0xAD to register description. New fields RESET_PLL2_DLD, PLL2_TSTMODE_REF_FB_EN, and PD_VCO_LDO.Go
- Added register 0xF6 to register description. New field PLL2_DLD_ENGo
- Added register 0xF7 to register description. New field PLL2_DUAL_LOOP_EN Go
- Changed Channel 5 and 6 FBClock Buffers from: Low Skew to: Zero Delay ModeGo
- Changed registers for WINDOW SIZE and LOCK COUNT. Updated equation to reflect the more general WINDOW SIZE and LOCK COUNT names and count frequency. Removed reference to holdover. Updated descriptive text Go
- Updated minimum lock time calculation example to reflect updated register names and count frequency Go
- Simplified HSDS format description Go
Changes from * Revision (January 2017) to A Revision
- 從 LMK04610 中刪除了 16 個差動 輸出 時鐘和 6 個頻率組特性Go
- 刪除了 LMK04610 中的 4 個基準(zhǔn)輸入特性Go
- 將文本從“–70dBc PSRR”更改為“–80dBc PSRR（在 VDDO 上）Go
- 將 SPI 接口默認(rèn)設(shè)置從 3 線制更改為 4 線制Go
- 將 VCO 頻率從“5.8GHz 至 6.2GHz”更改為“5.8GHz 至 6.175GHz”Go
- Changed VCO frequency from: 6200 MHz to: 6175 MHzGo
- Updated PLL1_CAP pin descriptionGo
- Removed tablenote from the doubler input frequency parameterGo
- Changed VCO tuning range maximum from: 6200 to: 6175Go
- Changed tablenote text from: ATE tested at 2949.12 MHz to: ATE tested at 258 MHzGo
- Removed the CLKin2/CLKin2*, and CLKin3/CLKin3* inputs from the LMK04610Go
- Updated the Functional Block DiagramGo
- Added content to the Driving CLKin and OSCin Pins With a Differential Source sectionGo
- Changed text from: Either AC coupling or DC coupling may be used. to: The clock is internally AC-coupled.Go
- Updated Figure 36Go
- Changed the tuning range of the oscillator from: 6200 MHz to: 6175 MHzGo
- Updated Figure 49Go
- Changed the caption title on Figure 53Go
- Changed the caption title on Figure 54Go
- Changed the caption title on Figure 55Go