ZHCSG17B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
The OUTCH10CNTRL2 Register controls Output CH10. Return to Register Map.
| BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| [7] | SYSREF_BYP_DYNDIGDLY_GATING_CH10 | RW | 0 | Bypass CH10 Dynamic Digital Delay Gating |
| [6] | SYSREF_BYP_ANALOGDLY_GATING_CH10 | RW | 0 | Bypass CH10 Analog Delay Gating |
| [5] | SYNC_EN_CH10 | RW | 0 | Output CH10 SYNC Enable |
| [4] | HS_EN_CH10 | RW | 0 | Output CH10 Enable Half-cycle delay |
| [3:2] | RSRVD | - | - | Reserved. |
| [1:0] | DRIV_10_SLEW[1:0] | RW | 0x0 | Slew Rate Setting OUTCH10. |