ZHCSG17B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
The OUTCH1CNTRL2 Register controls Output CH1. Return to Register Map.
| BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| [7] | SYSREF_BYP_DYNDIGDLY_GATING_CH1 | RW | 0 | Bypass CH1 Dynamic Digital Delay Gating |
| [6] | SYSREF_BYP_ANALOGDLY_GATING_CH1 | RW | 0 | Bypass CH1 Analog Delay Gating |
| [5] | SYNC_EN_CH1 | RW | 0 | Output CH1 SYNC Enable |
| [4] | HS_EN_CH1 | RW | 0 | Output CH1 Enable Half-cycle delay |
| [3:2] | DRIV_1_SLEW[1:0] | RW | 0x0 | Slew Rate Setting OUTCH1. |
| [1:0] | RSRVD | - | - | Reserved. |