ZHCSG17B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| fCLKin | Clock input frequency | Single-ended, DC-coupled (1) | 5 | 500 | MHz | ||
| Single-ended, AC-coupled (1) | 5 | 500 | |||||
| Differential, AC-coupled (2) | 5 | 600 | |||||
| SLEWDIFF | Differential input slew rate (3) | 20% to 80% | 0.2 | 6 | V/ns | ||
| SLEWSE | Single-ended input slew rate (3) | 20% to 80% | 0.1 | 3 | V/ns | ||
| VCLKin | Single-ended input voltage | DC-coupled to CLKinX;
CLKinX* AC-coupled to Ground |
0.5 | 3.3 | Vpp | ||
| AC-coupled to CLKinX;
CLKinX* AC-coupled to Ground |
0.5 | 3.3 | |||||
| VID,pp | Peak-to-peak differential input voltage (4)
See Figure 9 |
AC-coupled | 0.4 | 3.3 | Vpp | ||
| IDC | Input duty cycle | 45% | 50% | 55% | |||
| VNoise | Rejected input voltage noise during LOS condition | No LOS state change with single-ended, peak-to-peak input voltage noise injects to either CLKinX or CLKinX* or to both in phase.
Measured with 1-MHz sinusoidal signal |
40 | mV | |||