ZHCSG17B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
| PIN | I/O | TYPE | DESCRIPTION | |
|---|---|---|---|---|
| NAME | NO. | |||
| POWER | ||||
| DAP | DAP | GND | Die attach pad.
The DAP is an electrical connection and provides a thermal dissipation path. For proper electrical and thermal performance of the device, the DAP must be connected to the PCB ground plane. |
|
| VDD_CORE | 8 | P | 3.3-V power supply for core | |
| VDD_IO | 31 | P | 1.8-V to 3.3-V power supply for input block | |
| VDD_OSC | 37 | P | 1.8-V to 3.3-V power supply for OSCout | |
| VDD_PLL1 | 40 | P | 3.3-V power supply for PLL 1 | |
| VDD_PLL2CORE | 6 | P | 3.3-V power supply for PLL 2 | |
| VDD_PLL2OSC | 4 | P | 3.3-V power supply for PLL2 VCO | |
| VDDO_1/2 | 20 | P | 1.8-V to 3.3-V power supply for CLKout1 and CLKout2 | |
| VDDO_3/4 | 25 | P | 1.8-V to 3.3-V power supply for CLKout3 and CLKout4 | |
| VDDO_5 | 28 | P | 1.8-V to 3.3-V power supply for CLKout5 | |
| VDDO_6 | 43 | P | 1.8-V to 3.3-V power supply for CLKout6 | |
| VDDO_7/8 | 46 | P | 1.8-V to 3.3-V power supply for CLKout7 and CLKout8 | |
| VDDO_9/10 | 51 | P | 1.8-V to 3.3-V power supply for CLKout9 and CLKout10 | |
| PLL | ||||
| CTRL_VCXO | 41 | Analog | VCXO control output | |
| PLL1_CAP | 42 | Analog | PLL1 LDO capacitance - 10-µF external | |
| PLL2_LDO_CAP | 7 | Analog | PLL2 LDO capacitance - 10-µF external | |
| PLL2_VCO_LDO_CAP | 5 | Analog | PLL2 LDO capacitance - 10-µF external | |
| INPUT BLOCK | ||||
| CLKin_SEL | 34 | I | CMOS | Manual reference input selection for PLL1 weak pullup resistor. |
| CLKin0 | 33 | I | Analog | Reference clock input Port 0 for PLL1. |
| CLKin0* | 32 | |||
| CLKin1 | 30 | I | Analog | Reference clock input Port 1 for PLL1. |
| CLKin1* | 29 | |||
| OSCin | 39 | I | Analog | Feedback to PLL1, reference input to PLL2.
Accepts a differential or single-ended (VCXO) |
| OSCin* | 38 | |||
| OUTPUT BLOCK | ||||
| OSCout | 36 | O | Programmable | Buffered output of OSCin port. When using differential output mode, OSCout polarity is reversed from OSCin polarity. |
| OSCout* | 35 | |||
| CLKout1 | 16 | O | Programmable | Differential clock output pair 1. |
| CLKout1* | 17 | |||
| CLKout2 | 18 | O | Programmable | Differential clock output pair 2. |
| CLKout2* | 19 | |||
| CLKout3 | 21 | O | Programmable | Differential clock output pair 3. |
| CLKout3* | 22 | |||
| CLKout4 | 23 | O | Programmable | Differential clock output pair 4. |
| CLKout4* | 24 | |||
| CLKout5 | 26 | O | Programmable | Differential clock output pair 5. |
| CLKout5* | 27 | |||
| CLKout6 | 45 | O | Programmable | Differential clock output pair 6. |
| CLKout6* | 44 | |||
| CLKout7 | 48 | O | Programmable | Differential clock output pair 7. |
| CLKout7* | 47 | |||
| CLKout8 | 50 | O | Programmable | Differential clock output pair 8. |
| CLKout8* | 49 | |||
| CLKout9 | 53 | O | Programmable | Differential clock output pair 9. |
| CLKout9* | 52 | |||
| CLKout10 | 55 | O | Programmable | Differential clock output pair 10. |
| CLKout10* | 54 | |||
| DIGITAL CONTROL / INTERFACES | ||||
| NC | 1, 2, 3, 56 | Not connect pin | ||
| RESETN | 15 | I | CMOS | Device reset input |
| SCL | 13 | I | CMOS | SPI serial clock. |
| SCS* | 12 | I | CMOS | SPI serial chip select (active low). |
| SDIO | 11 | I/O | CMOS | SPI serial data input or output |
| STATUS0 | 9 | I/O | CMOS | Programmable status pin. See STATUS0/1 and SYNC Pin Functions for more details. |
| STATUS1 | 10 | I/O | CMOS | Programmable status pin. See STATUS0/1 and SYNC Pin Functions for more details. |
| SYNC | 14 | I/O | CMOS | Synchronization of output divider, definition of OSCout divider or programmable status pin. See STATUS0/1 and SYNC Pin Functions for more details. |