ZHCSG17B January 2017 – July 2019 LMK04610
PRODUCTION DATA.
The PLL2_CTRL2 Register provides control of PLL2 features. Return to Register Map.
| BIT NO. | FIELD | TYPE | RESET | DESCRIPTION |
|---|---|---|---|---|
| [7] | PLL2_BYP_SYNC_TOP | RW | 0 | RESERVED |
| [6] | PLL2_BYP_SYNC_BOTTOM | RW | 0 | RESERVED |
| [5] | PLL2_EN_BYP_BUF | RW | 0 | PLL2 Enable Bypass Clock Buffer. |
| [4] | PLL2_EN_BUF_SYNC_TOP | RW | 1 | PLL2 Enable Clock Buffer for Re-clocked SYNC signal to TOP Output-CHs. |
| [3] | PLL2_EN_BUF_SYNC_BOTTOM | RW | 1 | PLL2 Enable Clock Buffer for Re-clocked SYNC signal to Bottom Output-CHs. |
| [2] | PLL2_EN_BUF_OSCOUT | RW | 0 | PLL2 Enable Clock Buffer for OSCOut. |
| [1] | PLL2_EN_BUF_CLK_TOP | RW | 1 | PLL2 Enable Clock Buffer for Top Output-CHs. |
| [0] | PLL2_EN_BUF_CLK_BOTTOM | RW | 1 | PLL2 Enable Clock Buffer for Bottom Output-CHs. |