ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Vref = (VDD I/O)/2.
Figure 7-2 Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks.
Figure 7-3 Rise and Fall Transition Time Voltage Reference Levels