ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The switching characteristics and timing diagram for the DDR3 memory controller are shown in Table 8-42 and Figure 8-57.
| NO. | PARAMETER | MIN | MAX | UNIT | |
|---|---|---|---|---|---|
| 1 | tc(DDR_CLK) | Cycle time, DDR_CLK | 1.875 | 2.5(1) | ns |
Figure 8-57 DDR3 Memory Controller Clock Timing