ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the SYS_CLK1 clock input to the system. The external connections to support this are shown in Figure 6-4. The xi_osc0 pin is connected to the 1.8-V LVCMOS-Compatible clock source. The xi_osc0 pin is left unconnected. The vssa_osc0 pin is connected to board ground (VSS).
Figure 6-4 1.8-V LVCMOS-Compatible Clock Input Table 6-3 summarizes the OSC0 input clock electrical characteristics.
| NAME | DESCRIPTION | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| f | Frequency | 19.2, 20, 27 | MHz | ||
| CIN | Input capacitance | 2.184 | 2.384 | 2.584 | pF |
| IIN | Input current (3.3V mode) | 4 | 6 | 10 | µA |
Table 6-4 details the OSC0 input clock timing requirements.
| NAME | DESCRIPTION | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| CK0 | 1 / tc(xiosc0) | Frequency, xi_osc0 | 19.2, 20, 27 | MHz | |||
| CK1 | tw(xiosc0) | Pulse duration, xi_osc0 low or high |
0.45 * tc(xiosc0) |
0.55 * tc(xiosc0) | ns | ||
| tj(xiosc0) | Period jitter(1), xi_osc0 | 0.01 × tc(xiosc0) | ns | ||||
| tR(xiosc0) | Rise time, xi_osc0 | 5 | ns | ||||
| tF(xiosc0) | Fall time, xi_osc0 | 5 | ns | ||||
| tj(xiosc0) | Frequency accuracy(4), xi_osc0 | Ethernet and MLB not used | ±200 | ppm | |||
| Ethernet RGMII and RMII using derived clock | ±50 | ||||||
| Ethernet MII using derived clock | ±100 | ||||||
| MLB using derived clock | ±50 | ||||||
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
Figure 6-5 xi_osc0 Input Clock