ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
NOTE
For more information, see the Serial Communication Interface / Multimaster High-Speed I2C Controller / HS I2C Environment / HS I2C in I2C Mode section of the device TRM.
NOTE
I2C1 and I2C2 do NOT support HS-mode.
| SIGNAL NAME | DESCRIPTION | TYPE | BALL |
|---|---|---|---|
| Inter-Integrated Circuit Interface (I2C1) | |||
| i2c1_scl | I2C1 Clock | IOD | C20 |
| i2c1_sda | I2C1 Data | IOD | C21 |
| Inter-Integrated Circuit Interface (I2C2) | |||
| i2c2_scl | I2C2 Clock | IOD | F17 |
| i2c2_sda | I2C2 Data | IOD | C25 |
| Inter-Integrated Circuit Interface (I2C3) | |||
| i2c3_scl | I2C3 Clock | IOD | P7/ D14/ AB4/ F20 |
| i2c3_sda | I2C3 Data | IOD | N1/ C14/ AC5/ E21 |
| Inter-Integrated Circuit Interface (I2C4) | |||
| i2c4_scl | I2C4 Clock | IOD | R6/ J14/ A21/ Y9 |
| i2c4_sda | I2C4 Data | IOD | T9/ B14/ C18/ W7 |
| Inter-Integrated Circuit Interface (I2C5) | |||
| i2c5_scl | I2C5 Clock | IOD | AB9/ P6/F12 |
| i2c5_sda | I2C5 Data | IOD | AA3/ R9/G12 |