ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| NO. | PARAMETER | DESCRIPTION | SPEED | MIN | MAX | UNIT |
|---|---|---|---|---|---|---|
| 1 | tc(TX_CLK) | Cycle time, miin_txclk | 10 Mbps | 400 | ns | |
| 100 Mbps | 40 | ns | ||||
| 2 | tw(TX_CLKH) | Pulse duration, miin_txclk high | 10 Mbps | 140 | 260 | ns |
| 100 Mbps | 14 | 26 | ns | |||
| 3 | tw(TX_CLKL) | Pulse duration, miin_txclk low | 10 Mbps | 140 | 260 | ns |
| 100 Mbps | 14 | 26 | ns | |||
| 4 | tt(TX_CLK) | Transition time, miin_txclk | 10 Mbps | 3 | ns | |
| 100 Mbps | 3 | ns |
Figure 7-53 Clock Timing (GMAC Transmit) - MIIn operation Table 7-73 and Figure 7-54 present timing requirements for GMAC MIIn Receive 10/100Mbit/s.