ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Table 6-15 summarizes the DLL characteristics and assumes testing over recommended operating conditions.
| NAME | DESCRIPTION | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| finput | Input clock frequency (EMIF_DLL_FCLK) | 266 | MHz | ||
| tlock | Lock time | 50k | cycles | ||
| trelock | Relock time (a change of the DLL frequency implies that DLL must relock) | 50k | cycles |