ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Table 5-12 summarizes the DC electrical characteristics for IQ1833 Buffers.
| PARAMETER | MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| Signal Names in MUXMODE 0: tclk; | ||||||
| Balls: E20; | ||||||
| 1.8-V Mode | ||||||
| VIH | Input high-level threshold (Does not meet JEDEC VIH) | 0.75 * VDDS | V | |||
| VIL | Input low-level threshold (Does not meet JEDEC VIL) | 0.25 * VDDS | V | |||
| VHYS | Input hysteresis voltage | 100 | mV | |||
| IIN | Input current at each I/O pin | 2 | 11 | µA | ||
| CPAD | Pad capacitance (including package capacitance) | 1 | pF | |||
| 3.3-V Mode | ||||||
| VIH | Input high-level threshold (Does not meet JEDEC VIH) | 2.0 | V | |||
| VIL | Input low-level threshold (Does not meet JEDEC VIL) | 0.6 | V | |||
| VHYS | Input hysteresis voltage | 400 | mV | |||
| IIN | Input current at each I/O pin | 5 | 11 | µA | ||
| CPAD | Pad capacitance (including package capacitance) | 1 | pF | |||