ZHCSJ33F December 2015 – May 2019 DRA745 , DRA746 , DRA750 , DRA756
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
|---|---|---|---|---|---|
| 1 | tsu(RXD-RX_CLK) | Setup time, receive selected signals valid before miin_rxclk | 8 | ns | |
| tsu(RX_DV-RX_CLK) | |||||
| tsu(RX_ER-RX_CLK) | |||||
| 2 | th(RX_CLK-RXD) | Hold time, receive selected signals valid after miin_rxclk | 8 | ns | |
| th(RX_CLK-RX_DV) | |||||
| th(RX_CLK-RX_ER) |
Figure 7-54 GMAC Receive Interface Timing MIIn operation Table 7-74 and Figure 7-55 present timing requirements for GMAC MIIn Transmit 10/100Mbit/s.