SLVSJZ0 October 2025 MCF8316D-Q1
PRODUCTION DATA
Table 7-17 lists the memory-mapped registers for the Fault_Configuration registers. All register offset addresses not listed in Table 7-17 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 90h | FAULT_CONFIG1 | Fault Configuration1 | Section 7.2.1 |
| 92h | FAULT_CONFIG2 | Fault Configuration2 | Section 7.2.2 |
Complex bit access types are encoded to fit into small table cells. Table 7-18 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
FAULT_CONFIG1 is shown in Figure 7-15 and described in Table 7-19.
Return to the Summary Table.
Register to configure fault settings1
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PARITY | ILIMIT | HW_LOCK_ILIMIT | |||||
| R-0h | R/W-0h | R/W-0h | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| HW_LOCK_ILIMIT | LOCK_ILIMIT | EEP_FAULT_MODE | LOCK_ILIMIT_MODE | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| LOCK_ILIMIT_MODE | LOCK_ILIMIT_DEG | LCK_RETRY | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LCK_RETRY | CRC_ERR_MODE | MTR_LCK_MODE | IPD_TIMEOUT_FAULT_EN | IPD_FREQ_FAULT_EN | SATURATION_FLAGS_EN | ||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | PARITY | R | 0h | Parity bit |
| 30-27 | ILIMIT | R/W | 0h | Current limit for Iq axis (torque) current reference in closed loop
|
| 26-23 | HW_LOCK_ILIMIT | R/W | 0h | Comparator based lock detection current threshold
|
| 22-19 | LOCK_ILIMIT | R/W | 0h | ADC based lock detection current threshold
|
| 18 | EEP_FAULT_MODE | R/W | 0h | Fault response type for EEPROM fault
|
| 17-15 | LOCK_ILIMIT_MODE | R/W | 0h | Lock current limit mode
|
| 14-11 | LOCK_ILIMIT_DEG | R/W | 0h | Lock current limit detection deglitch time
|
| 10-7 | LCK_RETRY | R/W | 0h | Lock detection retry time
|
| 6 | CRC_ERR_MODE | R/W | 0h | CRC (in I2C communication) error mode
|
| 5-3 | MTR_LCK_MODE | R/W | 0h | Motor lock mode
|
| 2 | IPD_TIMEOUT_FAULT_EN | R/W | 0h | IPD timeout fault enable
|
| 1 | IPD_FREQ_FAULT_EN | R/W | 0h | IPD frequency fault enable
|
| 0 | SATURATION_FLAGS_EN | R/W | 0h | Enable indication of current loop and speed loop saturation
|
FAULT_CONFIG2 is shown in Figure 7-16 and described in Table 7-20.
Return to the Summary Table.
Register to configure fault settings2
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PARITY | LOCK1_EN | LOCK2_EN | LOCK3_EN | LOCK_ABN_SPEED | ABNORMAL_BEMF_THR | ||
| R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ABNORMAL_BEMF_THR | NO_MTR_THR | HW_LOCK_ILIMIT_MODE | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| HW_LOCK_ILIMIT_DEG | VOLTAGE_HYSTERESIS | MIN_VM_MOTOR | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MIN_VM_MODE | MAX_VM_MOTOR | MAX_VM_MODE | AUTO_RETRY_TIMES | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | PARITY | R | 0h | Parity bit |
| 30 | LOCK1_EN | R/W | 0h | Lock 1 (Abnormal Speed) Enable
|
| 29 | LOCK2_EN | R/W | 0h | Lock 2 (Abnormal BEMF) Enable
|
| 28 | LOCK3_EN | R/W | 0h | Lock 3 (No Motor) Enable
|
| 27-25 | LOCK_ABN_SPEED | R/W | 0h | Abnormal speed lock threshold (% of MAX_SPEED)
|
| 24-22 | ABNORMAL_BEMF_THR | R/W | 0h | Abnormal BEMF lock threshold (% of expected BEMF)
|
| 21-19 | NO_MTR_THR | R/W | 0h | No motor lock threshold
|
| 18-16 | HW_LOCK_ILIMIT_MODE | R/W | 0h | Hardware lock current limit mode
|
| 15-13 | HW_LOCK_ILIMIT_DEG | R/W | 0h | Hardware lock current limit detection deglitch time
|
| 12-11 | VOLTAGE_HYSTERESIS | R/W | 0h | Hysteresis for controller overvoltage and undervoltage faults. Fault triggered at threshold, cleared at threshold ± hysteresis (+ for UV, - for OV).
|
| 10-8 | MIN_VM_MOTOR | R/W | 0h | Controller under voltage fault threshold - minimum DC bus voltage for running motor
|
| 7 | MIN_VM_MODE | R/W | 0h | DC bus (controller) undervoltage fault recovery mode
|
| 6-4 | MAX_VM_MOTOR | R/W | 0h | Controller over voltage fault threshold - maximum DC bus voltage for running motor
|
| 3 | MAX_VM_MODE | R/W | 0h | DC bus (controller) overvoltage fault recovery mode
|
| 2-0 | AUTO_RETRY_TIMES | R/W | 0h | Number of automatic retry attempts
|