SLUSG51 October 2025 BQ25692-Q1
ADVANCE INFORMATION
Low ESR ceramic capacitors such as X7R or X5R are preferred for the decoupling capacitors and should be placed close to the converter VIN, SYS or SRN and GND pins. To account for a ceramic capacitor's de-rating due to temperature and applied voltage, the selected ceramic capacitor's voltage rating must be higher than the normal input voltage level. For example, a capacitor with 35V or higher voltage rating is preferred for up to 24V input voltage. Non-ceramic capacitors can be used if their ESR is less than 50mΩ. CVIN_ACP + CVIN_ACP must be at least 10uF after derating with CVIN_ACN < 4*CVIN_ACP. For 1S-2S applications, CSYS must be at least 15uF. For 3S-7S applications, CSYS must be at least 8uF after derating. CBAT, the bulk capacitance close to SRN and GND pins in parallel with the battery pack, must be at least 5uF after derating. The following sections explain how to size the derated capacitance value for the desired steady state voltage ripple. Voltage ripple is the highest for a buck converter's input and a boost converter's output. At a load transient step's start and release, additional capacitance may be required to reduce voltage dips and overshoot, respectively, for a buck, boost or buck-boost converter's output.