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ZHCSMZ6B December 2020 – July 2022 ADC3664

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSB|40
- MPQF185C

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSB|40
- QFND255H

訂購(gòu)信息

6.8 Timing Requirements

Typical values are over the operating free-air temperature range, at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and –1-dBFS differential input, unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
ADC Timing Specifications
t_AD	Aperture Delay			0.85		ns
t_A	Aperture Jitter	square wave clock with fast edges		250		fs
t_J	Jitter on DCLKIN				± 50	ps pk-pk
Recory time from +6 dB overload condition		SNR within 1 dB of expected value		1		Clock cycle
t_ACQ	Signal acquisition period	referenced to sampling clock falling edge		-T_S/4		Sampling clock period
t_CONV	Signal conversion period	referenced to sampling clock falling edge		6		ns
Wake up time	Time to valid data after coming out of power down. Internal reference.	Bandgap reference enabled, single ended clock		13		us
		Bandgap reference enabled, differential clock		15		us
		Bandgap reference disabled, single ended clock		2.4		ms
		Bandgap reference disabled, differential clock		2.3		ms
	Time to valid data after coming out of power down. External 1.6V reference.	Bandgap reference enabled, single ended clock		13		us
		Bandgap reference enabled, differential clock		14		us
		Bandgap reference disabled, single ended clock		2.0		ms
		Bandgap reference disabled, differential clock		2.2		ms
t_S,SYNC	Setup time for SYNC input signal	Referenced to sampling clock rising edge	500			ps
t_H,SYNC	Hold time for SYNC input signal	Referenced to sampling clock rising edge	600			ps
ADC Latency	Signal input to data output	1/2-wire SLVDS		1		Clock cycles
		1-wire SLVDS		1
		2-wire SLVDS		2
Add. Latency	Real decimation by 2			21		Output clock cycles
	Complex decimation by 2			22
	Real or complex decimation by 4, 8, 16, 32			23
Interface Timing: Serial LVDS Interface
t_PD	Propagation delay: sampling clock falling edge to DCLK rising edge	Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns. T_DCLK = DCLK period t_CDCLK = Sampling clock falling edge to DCLKIN falling edge	2 + T_DCLK + t_CDCLK	3 + T_DCLK + t_CDCLK	4 + T_DCLK + t_CDCLK	ns
t_PD		Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns. T_DCLK = DCLK period t_CDCLK = Sampling clock falling edge to DCLKIN falling edge	2 + t_CDCLK	3 + t_CDCLK	4 + t_CDCLK	ns
t_CD	DCLK rising edge to output data delay, 2-wire SLVDS, 14-bit	Fout = 65 MSPS, DA/B0,1 = 455 MBPS	0	0.1		ns
		Fout = 80 MSPS, DA/B0,1 = 560 MBPS	0	0.1
		Fout = 125 MSPS, DA/B0,1 = 875 MBPS	-0.2	0.1
	DCLK rising edge to output data delay, 1-wire SLVDS, 14-bit	Fout = 65 MSPS, DA/B0 = 910 MBPS	0	0.1
	DCLK rising edge to output data delay, 1-wire SLVDS, 16-bit	Fout = 10 MSPS, DA/B0 = 160 MBPS	0	0.1
		Fout = 25 MSPS, DA/B0 = 400 MBPS	0	0.1
		Fout = 62.5 MSPS, DA/B0= 1000 MBPS	-0.6	0.1
	DCLK rising edge to output data delay, 1/2-wire SLVDS, 16-bit	Fout = 5 MSPS, DA0 = 160 MBPS	0	0.1
		Fout = 10 MSPS, DA0 = 320 MBPS	0	0.1
		Fout = 25 MSPS, DA0 = 800 MBPS	0	0.1
t_DV	Data valid, 2-wire SLVDS, 14-bit	Fout = 65 MSPS, DA/B0,1 = 455 MBPS	1.8	1.9		ns
		Fout = 80 MSPS, DA/B0,1 = 560 MBPS	1.4	1.5
		Fout = 125 MSPS, DA/B0,1 = 875 MBPS	0.6	0.8
	Data valid, 1-wire SLVDS, 14-bit	Fout = 65 MSPS, DA/B0 = 910 MBPS	0.6	0.8
	Data valid, 1-wire SLVDS, 16-bit	Fout = 10 MSPS, DA/B0 = 160 MBPS	5.7	5.8
		Fout = 25 MSPS, DA/B0 = 400 MBPS	2.0	2.1
		Fout = 62.5 MSPS, DA/B0= 1000 MBPS	0.5	0.6
	Data valid, 1/2-wire SLVDS, 16-bit	Fout = 5 MSPS, DA0 = 160 MBPS	5.7	5.8
		Fout = 10 MSPS, DA0 = 320 MBPS	2.7	2.8
		Fout = 25 MSPS, DA0 = 800 MBPS	0.8	0.9
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
f_CLK,SCLK	Serial clock frequency				20	MHz
t_S,SEN	SEN falling edge to SCLK rising edge		10			ns
t_H,SEN	SCLK rising edge to SEN rising edge		9
t_S,SDIO	SDIO setup time from rising edge of SCLK		17
t_H,SDIO	SDIO hold time from rising edge of SCLK		9
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
t_OZD	Delay from falling edge of 16th SCLK cycle during read operation for SDIO transition from tri-state to valid data		3.9		10.8	ns
t_ODZ	Delay from SEN rising edge for SDIO transition from valid data to tri-state		3.4		14
t_OD	Delay from falling edge of 16th SCLK cycle during read operation to SDIO valid		3.9		10.8