ZHCSMZ6B December 2020 – July 2022 ADC3664
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics - Power Consumption
- 6.6 Electrical Characteristics - DC Specifications
- 6.7 Electrical Characteristics - AC Specifications
- 6.8 Timing Requirements
- 6.9 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application Information Disclaimer
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSB|40
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSB|40
訂購信息
5 Pin Configuration and Functions
Figure 5-1 RSB (WQFN) Package, 40-Pin(Top View)
Table 5-1 Pin Descriptions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| INPUT/REFERENCE | |||
| AINM | 13 | I | Negative analog input, channel A |
| AINP | 12 | I | Positive analog input, channel A |
| BINP | 39 | I | Positive analog input, channel B |
| BINM | 38 | I | Negative analog input, channel B |
| REFBUF | 4 | I | 1.2 V external voltage reference input for use with internal reference buffer. Internal 100 kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions. |
| REFGND | 3 | I | Reference ground input, 0 V |
| VCM | 8 | O | Common-mode voltage output for the analog inputs, 0.95V |
| VREF | 2 | I | External voltage reference input |
| CLOCK | |||
| CLKM | 7 | I | Negative differential sampling clock input for the ADC |
| CLKP | 6 | I | Positive differential sampling clock input for the ADC |
| CONFIGURATION | |||
| PDN/SYNC | 1 | I | Power down/Synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor. |
| RESET | 9 | I | Hardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor. |
| SCLK | 35 | I | Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor. |
| SDIO | 10 | I | Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor. |
| SEN | 16 | I | Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD. |
| NC | 27 | - | Do not connect |
| DIGITAL INTERFACE | |||
| DA0P | 20 | O | Positive differential serial LVDS output for lane 0, channel A. |
| DA0M | 19 | O | Negative differential serial LVDS output for lane 0, channel A. |
| DA1P | 18 | O | Positive differential serial LVDS output for lane 1, channel A. |
| DA1M | 17 | O | Negative differential serial LVDS output for lane 1, channel A. |
| DB0P | 31 | O | Positive differential serial LVDS output for lane 0, channel B. |
| DB0M | 32 | O | Negative differential serial LVDS output for lane 0, channel B. |
| DB1P | 33 | O | Positive differential serial LVDS output for lane 1, channel B. |
| DB1M | 34 | O | Negative differential serial LVDS output for lane 1, channel B. |
| DCLKP | 23 | O | Positive differential serial LVDS bit clock output. |
| DCLKM | 22 | O | Negative differential serial LVDS bit clock output. |
| FCLKP | 28 | O | Positive differential serial LVDS frame clock output. |
| FCLKM | 29 | O | Negative differential serial LVDS frame clock output. |
| DCLKINP | 25 | I | Positive differential serial LVDS bit clock input. Internal 100 Ω differential termination. |
| DCLKINM | 24 | I | Negative differential serial LVDS bit clock input. Internal 100 Ω differential termination. |
| POWER SUPPLY | |||
| AVDD | 5,15,36 | I | Analog 1.8-V power supply |
| GND | 11,14,37,40, PowerPAD | I | Ground, 0 V |
| IOGND | 26 | I | Ground, 0 V for digital interface |
| IOVDD | 21,30 | I | 1.8-V power supply for digital interface |