ZHCSMZ6B December 2020 – July 2022 ADC3664
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics - Power Consumption
- 6.6 Electrical Characteristics - DC Specifications
- 6.7 Electrical Characteristics - AC Specifications
- 6.8 Timing Requirements
- 6.9 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application Information Disclaimer
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSB|40
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RSB|40
訂購信息
8.3.4.7 Output Formatting with Decimation
When using decimation, the output data is formatted as shown in Figure 8-32 and Figure 8-33. The examples are shown for 16-bit output for 2-wire (8x serialization), 1-wire (16x serialization) and 1/2-wire (32x serialization).
Figure 8-32 Output Data Format in Complex DecimationTable 8-3 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK frequencies based on output resolution (R), number of SLVDS lanes (L) and complex decimation setting (N).
Furthermore the table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 16-bit output resolution and complex decimation by 4.
| DECIMATION SETTING | ADC SAMPLING RATE | OUTPUT RESOLUTION | # of WIRES | FCLK | DCLKIN, DCLK | DA/B0,1 |
|---|---|---|---|---|---|---|
| N | FS | R | L | FS / N | [DA/B0,1] / 2 | FS x 2 x R / L / N |
| 4 | 125 MSPS | 16 | 2 | 31.25 MHz | 250 MHz | 500 MHz |
| 1 | 500 MHz | 1000 MHz | ||||
| 55 MSPS | 1/2 | 15.625 MHz | 500 MHz | 1000 MHz |
Figure 8-33 Output Data Format in Real DecimationTable 8-4 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK frequencies based on output resolution (R), number of SLVDS lanes (L) and real decimation setting (M).
Furthermore the table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 16-bit output resolution and real decimation by 4.
| DECIMATION SETTING | ADC SAMPLING RATE | OUTPUT RESOLUTION | # of WIRES | FCLK | DCLKIN, DCLK | DA/B0,1 |
|---|---|---|---|---|---|---|
| M | FS | R | L | FS / M / 2 (L = 2) FS / M (L = 1, 1/2) | [DA/B0,1] / 2 | FS x R / L / M |
| 4 | 125 MSPS | 16 | 2 | 15.625 MHz | 125 MHz | 250 MHz |
| 1 | 31.25 MHz | 250 MHz | 500 MHz | |||
| 1/2 | 500 MHz | 1000 MHz |