中字幕视频在线永久在线,狼人大香伊蕉国产WWW亚洲

ZHCSMZ6B December 2020 – July 2022 ADC3664

PRODUCTION DATA

封裝選項

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSB|40
- MPQF185C

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSB|40
- QFND255H

訂購信息

6.6 Electrical Characteristics - DC Specifications

Typical values are over the operating free-air temperature range, at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and –1-dBFS differential input, unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DC ACCURACY
No missing codes			14			bits
PSRR		F_IN = 1 MHz		35		dB
DNL	Differential nonlinearity	F_IN = 5 MHz	-0.97	± 0.9	0.97	LSB
INL	Integral nonlinearity	F_IN = 5 MHz	-7.5	± 2.6	7.5	LSB
V_{OS_ERR}	Offset error		-55	± 30	55	LSB
V_{OS_DRIFT}	Offset drift over temperature			± 0.06		LSB/oC
GAIN_ERR	Gain error	External 1.6V Reference		± 2		%FSR
GAIN_DRIFT	Gain drift over temperature	External 1.6V Reference		± 57		ppm/oC
GAIN_ERR	Gain error	Internal Reference		± 3		%FSR
GAIN_DRIFT	Gain drift over temperature	Internal Reference		106		ppm/oC
Transition Noise				0.7		LSB
ADC ANALOG INPUT (AINP/M, BINP/M)
FS	Input full scale	Differential		3.2		Vpp
V_CM	Input common model voltage		0.9	0.95	1.0	V
R_IN	Input resistance	Differential at DC		8		kΩ
C_IN	Input Capacitance	Differential at DC		5.4		pF
V_OCM	Output common mode voltage			0.95		V
BW	Analog Input Bandwidth (-3dB)			1.4		GHz
Internal Voltage Reference
V_REF	Internal reference voltage			1.6		V
V_REFOutput Impedance				8		Ω
Reference Input Buffer (REFBUF)
External reference voltage				1.2		V
External voltage reference (VREF)
V_REF	External voltage reference			1.6		V
Input Current				1		mA
Input impedance				5.3		kΩ
Clock Input (CLKP/M)
Input clock frequency		External reference	0.5		125	MHz
Input clock frequency		Internal reference	100		125	MHz
V_ID	Differential input voltage			1	3.6	Vpp
V_CM	Input common mode voltage			0.9		V
R_IN	Single ended input resistance to common mode			5		kΩ
C_IN	Single ended input capacitance			1.5		pF
Clock duty cycle			45	50	60	%
Digital Inputs (RESET, PDN, SCLK, SEN, SDIO)
V_IH	High level input voltage		1.4			V
V_IL	Low level input voltage				0.4	V
I_IH	High level input current			90	150	uA
I_IL	Low level input current		-150	-90		uA
C_I	Input capacitance			1.5		pF
Digital Output (SDOUT)
V_OH	High level output voltage	I_LOAD = -400 uA	IOVDD – 0.1	IOVDD		V
V_OL	Low level output voltage	I_LOAD = 400 uA			0.1	V
SLVDS Interface
V_ID	Differential input voltage	DCLKIN	200	350	650	mVpp
V_CM	Input common mode voltage	DCLKIN	1	1.2	1.3	V
Output data rate		per differential SLVDS output			1	Gbps
V_OD	Differential output voltage		500	700	850	mVpp
V_CM	Output common mode voltage			1.0		V