ZHCSMZ6B December 2020 – July 2022 ADC3664
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics - Power Consumption
- 6.6 Electrical Characteristics - DC Specifications
- 6.7 Electrical Characteristics - AC Specifications
- 6.8 Timing Requirements
- 6.9 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application Information Disclaimer
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RSB|40
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RSB|40
訂購信息
9.4.2 Layout Example
The following screen shot shows the top layer of the ADC366x EVM.
- Signal and clock inputs are routed as differential signals on the top layer avoiding vias.
- SLVDS output interface lanes are routed differential and length matched
- Bypass caps are close to the VREF pin on the top layer avoiding vias.
Figure 9-10 Layout example: top layer of ADC366x EVM