ZHCSO96B June 2021 – June 2022 DAC12DL3200
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| LATENCY | ||||||
| TDAC | DAC sampling period | 1 / fCLK | s | |||
| tLAT | digital input to DAC output sample latency | single clock mode, 4 LVDS banks for 1 DAC | 35.5 | TDAC | ||
| single clock mode, 2 LVDS banks per DAC | 20.5 | |||||
| single clock mode, 1 LVDS bank per DAC | 12.5 | |||||
| dual clock mode, 2 LVDS banks per DAC | 35.5 | |||||
| dual clock mode, 1 LVDS bank per DAC | 20.5 | |||||
| tPDI | Input clock rising edge cross-over to output sample cross-over | 680 | ps | |||
| SERIAL PROGRAMMING INTERFACE | ||||||
| Fs_c_r | serial clock frequency reading | 100 | MHz | |||
| Fs_c_w | serial clock frequency writing | 200 | MHz | |||
| Fs_cts | serial clock frequency temp sensor | 1 | MHz | |||
| tP_W | serial clock period for writing | 5 | ns | |||
| tP_R | serial clock period for reading | 10 | ns | |||
| tPH | serial clock pulse width high | 2 | ns | |||
| tPL | serial clock pulse width low | 2 | ns | |||
| tSU | SDI setup | 1 | ns | |||
| tH | SDI hold | 1 | ns | |||
| tIZ | SDI TRI-STATE | 1 | ns | |||
| tODZ | SDO driven to TRI-STATE | 200 fF load | 0 | 1.5 | ns | |
| tOZD | SDO TRI-STATE to driven | 200 fF load | 0 | 1.5 | ns | |
| tOD | SDO output delay | 200 fF load | 0 | 6 | ns | |
| tCSS | SCS setup | 1 | ns | |||
| tCSH | SCS hold | 1 | ns | |||
| tIAG | Inter-access gap | 1 | ns | |||