ZHCSO96B June 2021 – June 2022 DAC12DL3200
PRODUCTION DATA
DAC12DL3200 uses a source-synchronous interface to simplify signal timing. The DDR data clocks are sent from the logic device along with the data such that propagation delays through the logic device and receiving DAC are well matched over all process, voltage and temperature variations. Test patterns can be used to verify proper timing at all LVDS input receivers. Internal FIFOs absorb skew between the data clock domains before being aligned to the DAC sampling clock domain (DACCLK). Each LVDS data bus should have matched trace lengths relative to the associated data clock (e.g. DACLK for bus A), however each bus does not have to be trace length matched to the others due to the internal FIFOs. For example, the signals for bus A (DACLK, DASTR, DA0…11) should be matched in length, but they do not need to be length matched to the signals for bus B.