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ZHCSO96B June 2021 – June 2022 DAC12DL3200

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

ACF|256
- MPBGAO1C
ALJ|256
- MPBGAS8B

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.5 Electrical Characteristics - DC Specifications

Typical values at T_A = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, single channel (MODE2) at 6.4 GSPS, RF mode, I_OUTFS = 20.5mA, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DC ACCURACY
BITS	DAC core resolution⁽¹⁾		16			bits
DNL	Differential nonlinearity	LVDS input with 12-bit resolution (1 LSB = Fullscale/4096)		±0.6		LSB
INL	Integral nonlinearity	LVDS input with 12-bit resolution (1 LSB = Fullscale/4096)		±0.9		LSB
DAC ANALOG OUTPUT (IOUTA+, IOUTA–, IOUTB+, IOUTB–)
P_OUTFS	Output power	DACFS = 0xF, NRZ mode, 6.4 Gsps, f_OUT = 397 MHz, measured into 100-Ω load⁽⁵⁾⁽⁴⁾		1.4		dBm
I_FS	Switched full scale output current⁽²⁾	3.6-k? resistor from RBIAS to AGND, COARSE_CUR_A/B = 0xF and FINE_CUR_A/FINE_CUR_B = 0x1F		20.5		mA
I_FS	Switched full scale output current⁽²⁾	3.6-k? resistor from RBIAS to AGND, COARSE_CUR_A/B = 0x0 and FINE_CUR_A/FINE_CUR_B = 0x00		5.2		mA
I_FSDRIFT	Full scale output current temperature drift	3.6-k? resistor from RBIAS to AGND, COARSE_CUR_A/B = 0xF and FINE_CUR_A/FINE_CUR_B = 0x1F		0.6		uA/℃
I_FSDRIFT	Full scale output current temperature drift			23		PPM/℃
V_COMP	Output compliance voltage range	Meaured from VOUTA+, VOUTA–, VOUTB+ or VOUTB– to AGND	1.3		2.3	V
C_OUT	Output capacitance	Single-ended capacitance to ground		0.04		pF
R_TERM	Output differential termination resistance			109		Ω
R_TERMDRIFT	Output differential termination resistance temperature coeff			-0.13		mΩ/℃
R_TERMDRIFT				-133		PPM/℃
CLOCK AND SYSREF INPUTS (CLKIN+, CLKIN-, SYSREF+, SYSREF-)
R_T	Internal differential termination resistance			107		Ω
V_CM	Input common mode voltage			0.5		V
C_IN	Internal differential input capacitance			0.5		pF
REFERENCE OUTPUT (EXTIO)
V_REF	Reference output voltage			0.9		V
V_REF-DRIFT	Reference output voltage drift over temperature			±34		ppm/°C
I_REF	Maximum reference output current sourcing capability			100		nA
LVDS INTERFACE (DAx±, DBx±, DCx±, DDx±, DxSTR±, DCLKx±)
R_T	Internal differential termination resistance			115		Ω
CMOS INTERFACE (SCLK, SCS, SDI, SDO, RESET, NCOBANKSEL, NCOSEL[0:3], SLEEP, SYNC)
I_IH	High level input current	High level input current⁽⁶⁾			200	uA
I_IL	Low level input current	Low level input current⁽⁶⁾	-200			uA
V_IH	High level input voltage	SCLK, SCS, SDI, RESET, NCOBANKSEL, NCOSEL[0:3], SLEEP, SYNC, TESTMODE, TXENABLE⁽³⁾	0.7 x VDDIO18			V
V_IL	Low level input voltage	SCLK, SCS, SDI, RESET, NCOBANKSEL, NCOSEL[0:3], SLEEP, SYNC, TESTMODE, TXENABLE⁽³⁾			0.3 x VDDIO18	V
C_I	Input capacitance	Input capacitance		2		pF
V_OH	High level output voltage	I_LOAD = –400 uA	1.55			V
V_OL	Low level output voltage	I_LOAD = 400 uA			0.25	V
TEMPERATURE SENSOR
Res	Resolution			8		bits
Range	Digital Range		-64		127	℃
T_ERROR	Temperature Error	TA = 25℃, device powered down except for temperature sensor and SPI interface		±5		℃

(1) When using LVDS input, the resolution is limited by the LVDS interface to 12-bits. 16-bits only applies when using the NCO.

(2) In addition to the switched full scale output current, each output (VOUTA+, VOUTA-, VOUTB+, VOUTB-) has a fixed output current of ~ 3mA at a coarse DAC setting of 15.

(3) Measured to DGND.

(4) See DAC Output Modes for information on the frequency response of different DAC output modes. Output power vs frequency for different modes relative to NRZ mode at low frequency is shown in Figure 6-3 through Figure 6-8

(5) A 100? load is equivalent to a 2:1 with 50? single ended load

(6) With no IO supply voltage offset in connecting device.