The SYSREF windowing block is used to first detect the position of SYSREF relative to the DEVCLK rising edge and then to select a desired SYSREF sampling instance, to maximize setup and hold timing margins. In many cases a single SYSREF sampling position (SYSREF_SEL) is sufficient to meet timing for all systems (part-to-part variation) and conditions (temperature and voltage variations). However, the feature can also be used by the system to expand the timing window by tracking the movement of SYSREF as operating conditions change or to remove system-to-system variation at production test by finding a unique optimal value at nominal conditions for each system.

Use of the SYSREF windowing block is as follows. First, the device clock and SYSREF should be applied to the device. The location of SYSREF relative to the device clock cycle is determined and stored in SYSREF_POS. Each bit of SYSREF_POS represents a potential SYSREF sampling position. If a bit in SYSREF_POS is set to '1', then the corresponding SYSREF sampling position has a potential setup or hold violation. Upon determining the valid SYSREF sampling positions (the positions of SYSREF_POS that are set to '0') the desired sampling position can be chosen by setting SYSREF_SEL to the value corresponding to that SYSREF_POS position. In general the middle sampling position between two setup and hold instances should be chosen. Ideally, SYSREF_POS and SYSREF_SEL should be performed at the system's nominal operating conditions (temperature and supply voltage) to provide maximum margin for operating condition variations. This process can be performed at final test and the optimal SYSREF_SEL setting can be stored for use at every system power up. Further, SYSREF_POS can be used to characterize the skew between DEVCLK and SYSREF over operating conditions for a system by sweeping the system temperature and supply voltages. For systems that have large variations in DEVCLK to SYSREF skew this characterization can be used to track the optimal SYSREF sampling position as system operating conditions change. In general, a single value can be found that meets timing over all conditions for well matched systems, such as those where DEVCLK and SYSREF come from a single clocking device.

The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When SYSREF_ZOOM is set to '0', the delay steps are more coarse. When SYSREF_ZOOM is set to '1', the delay steps finer steps. In general, SYSREF_ZOOM should always be used ( SYSREF_ZOOM = 1) unless a transition region (defined by 1's in SYSREF_POS) is not seen, which is possible for low clock rates. Bits 0 and 15 of SYSREF_POS will always be set to '1' since it cannot be determined if these settings are close to a timing violation, although the actual valid window could extend beyond these sampling positions. The value programmed into SYSREF_SEL is the decimal number representing the desired bit location in SYSREF_POS.

The table below shows some example SYSREF_POS readings and the optimal SYSREF_SEL settings. In general, lower values of SYSREF_SEL should be selected due to variation of the delays over supply voltage, however in the second example a value of 8 provides additional margin and may be selected instead.

1. Apply SYSREF and DEVCLK
2. Set SYSREF_RECV_SLEEP=0, SYSREF_POS_SEL=0, and SYSREF_ZOOM=1
3. Set SYSREF_PROC_EN=1
4. Read SYSREF_POS and determine proper setting for SYSREF_SEL. If proper sampling point cannot be determined, set SYSREF_ZOOM=0 and retry.

The SYSREF_POS register can report either an accumulation of all the SYSREF edges seen since SYSREF_PS_EN transitioned from 0 to 1 (infinite persistence) or just the last SYSREF edge (when SYSREF_PS_EN=0). The user should reset the persistence after changing SYSREF_POS_SEL.