9 Revision History
Changes from Revision B (December 2023) to Revision C (July 2025)
- 更新了整個(gè)文檔中的印刷錯(cuò)誤并澄清了文本。將 UCC28070 信息并入 UCC28070A 資料表。Go
- 修訂了特性和應(yīng)用要點(diǎn)。添加了超鏈接。Go
- Added Wide-SOIC package pin-out view for UCC28070Go
- Linked device numbers to respective DW and PW package thermal
information.Go
- Linked device numbers to respective fPWM limits.Go
- Include UCC28070 at all mentions of UCC28070A throughout the data
sheet.Go
- Updated tSYNC meaning; added reference to minimum allowable pulse
widthGo
- Added falling thresholds to VINAC levels table.Go
- Option in text for using ? fPWM in Cpc equation. Changed equation
to match calculator tool.Go
- Remove extra factor of 2 from Io_ripple equationGo
- Corrections to equations for Rta and CtaGo
Changes from Revision A (May 2016) to Revision B (December 2023)
- 更新了整個(gè)文檔中的印刷錯(cuò)誤并澄清了文本。Go
- Moved Absolute Maximum values for Supply voltage and current,
Gate-drive currents, and signal-pin Currents from MIN column to MAX column Go
- Updated Y-axis units in several figuresGo
- Added SYNC frequency limitation note in External Clock
Synchronization sectionGo
- Added paragraph on PKLMT sub-harmonic oscillationGo
- Added clarifying equation for kSYNC in Current Loop Compensation
section; corrected gain in Current Error Amplifier diagram and equation for Rzc. Go
- Updated gain in Voltage Error Amplifier diagram Go
- Updated text to clarify bridge
rectifier design considerationsGo
- Updated method for calculating boost inductanceGo
- 在“相關(guān)文檔”部分添加了其他參考Go