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ZHCS779C March 2012 – July 2025 UCC28070 , UCC28070A

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

PW|20
- MPDS362A

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.3.4 External Clock Synchronization

The UCC28070A has also been designed to be easily synchronized to almost any external frequency source. By disabling frequency dithering (pulling CDR > 5V), the SYNC circuitry is enabled permitting the internal oscillator to be synchronized with pulses presented on the RDM pin. To ensure that a precise 180° phase shift is maintained between the GDA and GDB outputs, the frequency (f_SYNC) of the pulses presented at the RDM pin must be at twice the desired f_PWM. For example, if a PWM switching frequency of 100kHz is desired, the f_SYNC must be 200kHz.

Equation 7.

f_{P W M} = \frac{f_{S Y N C}}{2}, t h e r e f o r e f_{S Y N C} = 2 \times f_{P W M}

To ensure the internal oscillator does not interfere with the SYNC function, R_RT must be sized to set the internal oscillator frequency about 10% below the minimum expected f_SYNC.

Equation 8. UCC28070 UCC28070A

It must be noted that the PWM modulator gain is reduced by a factor equivalent to the scaled R_RT due to a direct correlation between the PWM ramp current and R_RT. Adjustments to the current-loop gains must be made accordingly, using the k_SYNC factor as indicated in Current Loop Compensation.

It must also be noted that the maximum duty-cycle clamp programmability is affected during external synchronization. The internal timing circuitry responsible for setting the maximum duty cycle is initiated on the falling edge of the synchronization pulse. Therefore, the selection of R_DMX becomes dependent on the synchronization pulse width (t_SYNC). In this context, t_SYNC is a pulse width; t_SYNC is not the inverse of f_SYNC.

Equation 9. UCC28070 UCC28070A

(For use in R_DMX equation immediately below.)

Equation 10. UCC28070 UCC28070A

Consequently to minimize the impact of the t_SYNC it is clearly advantageous to use the smallest synchronization pulse width feasible (see Electrical Characteristics Table for minimum allowable pulse width).

Note:

When external synchronization is used, a propagation delay of approximately 50ns to 100ns exists between internal timing circuits and the falling edge of the SYNC signal, which may result in reduced OFF-time at the highest of switching frequencies. Therefore, at high SYNC frequencies R_DMX value must be adjusted downward slightly by (t_SYNC – 0.1μs) / t_SYNC to compensate. At lower SYNC frequencies, this delay becomes an insignificant fraction of the PWM period, and can be neglected.

Note:

The oscillator in the UCC28070A device is not designed to accommodate wide variations in the external SYNC frequency. Do not allow the SYNC frequency variation to exceed ±10% of the nominal f_SYNC as used in Equation 8. Excessive variation of f_SYNC can cause malfunction of the controller to occur. R_RT value must be calculated at the lowest f_SYNC.