ZHCS986B May 2012 – December 2018 TLV320DAC3203
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 描述
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics, Bypass Outputs
- 6.6 Electrical Characteristics, Microphone Interface
- 6.7 Electrical Characteristics, Audio Outputs
- 6.8 Electrical Characteristics, LDO
- 6.9 Electrical Characteristics, Misc.
- 6.10 Electrical Characteristics, Logic Levels
- 6.11 Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S)
- 6.12 Typical DSP Timing Characteristics
- 6.13 I2C Interface Timing
- 6.14 SPI Interface Timing (See )
- 6.15 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
訂購信息
6.14 SPI Interface Timing (See Figure 6)
All specifications at 25°C, DVdd = 1.8V| IOVDD=1.8V | IOVDD=3.3V | UNITS | |||||||
|---|---|---|---|---|---|---|---|---|---|
| MIN | TYP | MAX | MIN | TYP | MAX | ||||
| tsck | SCLK Period | 100 | 50 | ns | |||||
| tsckh | SCLK Pulse width High | 50 | 25 | ns | |||||
| tsckl | SCLK Pulse width Low | 50 | 25 | ns | |||||
| tlead | Enable Lead Time | 30 | 20 | ns | |||||
| tlag | Enable Lag Time | 30 | 20 | ns | |||||
| td;seqxfr | Sequential Transfer Delay | 40 | 20 | ns | |||||
| ta | Slave DOUT access time | 40 | 20 | ns | |||||
| tdis | Slave DOUT disable time | 40 | 25 | ns | |||||
| tsu | DIN data setup time | 15 | 10 | ns | |||||
| th;DIN | DIN data hold time | 15 | 10 | ns | |||||
| tv;DOUT | DOUT data valid time | 45 | 25 | ns | |||||
| tr | SCLK Rise Time | 4 | 4 | ns | |||||
| tf | SCLK Fall Time | 4 | 4 | ns | |||||
Figure 6. SPI Interface Timing Diagram