ZHCS986B May 2012 – December 2018 TLV320DAC3203
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 描述
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics, Bypass Outputs
- 6.6 Electrical Characteristics, Microphone Interface
- 6.7 Electrical Characteristics, Audio Outputs
- 6.8 Electrical Characteristics, LDO
- 6.9 Electrical Characteristics, Misc.
- 6.10 Electrical Characteristics, Logic Levels
- 6.11 Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S)
- 6.12 Typical DSP Timing Characteristics
- 6.13 I2C Interface Timing
- 6.14 SPI Interface Timing (See )
- 6.15 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
訂購信息
6.13 I2C Interface Timing
| Standard-Mode | Fast-Mode | UNITS | |||||||
|---|---|---|---|---|---|---|---|---|---|
| MIN | TYP | MAX | MIN | TYP | MAX | ||||
| fSCL | SCL clock frequency | 0 | 100 | 0 | 400 | kHz | |||
| tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated. | 4.0 | 0.8 | μs | |||||
| tLOW | LOW period of the SCL clock | 4.7 | 1.3 | μs | |||||
| tHIGH | HIGH period of the SCL clock | 4.0 | 0.6 | μs | |||||
| tSU;STA | Setup time for a repeated START condition | 4.7 | 0.8 | μs | |||||
| tHD;DAT | Data hold time: For I2C bus devices | 0 | 3.45 | 0 | 0.9 | μs | |||
| tSU;DAT | Data set-up time | 250 | 100 | ns | |||||
| tr | SDA and SCL Rise Time | 1000 | 20+0.1Cb | 300 | ns | ||||
| tf | SDA and SCL Fall Time | 300 | 20+0.1Cb | 300 | ns | ||||
| tSU;STO | Set-up time for STOP condition | 4.0 | 0.8 | μs | |||||
| tBUF | Bus free time between a STOP and START condition | 4.7 | 1.3 | μs | |||||
| Cb | Capacitive load for each bus line | 400 | 400 | pF | |||||
Figure 5. I2C Interface Timing