ZHCS986B May 2012 – December 2018 TLV320DAC3203
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 描述
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics, Bypass Outputs
- 6.6 Electrical Characteristics, Microphone Interface
- 6.7 Electrical Characteristics, Audio Outputs
- 6.8 Electrical Characteristics, LDO
- 6.9 Electrical Characteristics, Misc.
- 6.10 Electrical Characteristics, Logic Levels
- 6.11 Typical Timing Characteristics — Audio Data Serial Interface Timing (I2S)
- 6.12 Typical DSP Timing Characteristics
- 6.13 I2C Interface Timing
- 6.14 SPI Interface Timing (See )
- 6.15 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
訂購信息
6.12 Typical DSP Timing Characteristics
All specifications at 25°C, DVdd = 1.8V| IOVDD=1.8V | IOVDD=3.3V | UNITS | ||||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| DSP Timing in Master Mode (see Figure 3) | ||||||
| td (WS) | WCLK delay | 30 | 20 | ns | ||
| td (DO-BCLK) | BCLK to DOUT delay | 40 | 20 | ns | ||
| ts(DI) | DIN setup | 8 | 8 | ns | ||
| th(DI) | DIN hold | 8 | 8 | ns | ||
| tr | Rise time | 24 | 12 | ns | ||
| tf | Fall time | 24 | 12 | ns | ||
| DSP Timing in Slave Mode (see Figure 4) | ||||||
| tH (BCLK) | BCLK high period | 35 | 35 | ns | ||
| tL (BCLK) | BCLK low period | 35 | 35 | ns | ||
| ts(WS) | WCLK setup | 8 | 8 | ns | ||
| th(WS) | WCLK hold | 8 | 8 | ns | ||
| td (DO-BCLK) | BCLK to DOUT delay | 40 | 22 | ns | ||
| ts(DI) | DIN setup | 8 | 8 | ns | ||
| th(DI) | DIN hold | 8 | 8 | ns | ||
| tr | Rise time | 4 | 4 | ns | ||
| tf | Fall time | 4 | 4 | ns | ||
Figure 3. DSP Timing in Master Mode 
Figure 4. DSP Timing in Slave Mode