SLLSFV1 March 2025 MCF8329A-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Three Phase BLDC Gate Drivers
- 6.3.2 Gate Drive Architecture
- 6.3.3 AVDD Linear Voltage Regulator
- 6.3.4 Low-Side Current Sense Amplifier
- 6.3.5 Device Interface Modes
- 6.3.6 Motor Control Input Options
- 6.3.7 Bootstrap Capacitor Initial Charging
- 6.3.8 Starting the Motor Under Different Initial Conditions
- 6.3.9 Motor Start Sequence (MSS)
- 6.3.10 Closed Loop Operation
- 6.3.11 Maximum Torque Per Ampere (MTPA) Control
- 6.3.12 Flux Weakening Control
- 6.3.13 Motor Parameters
- 6.3.14 Motor Parameter Extraction Tool (MPET)
- 6.3.15 Anti-Voltage Surge (AVS)
- 6.3.16 Active Braking
- 6.3.17 Output PWM Switching Frequency
- 6.3.18 Dead Time Compensation
- 6.3.19 Voltage Sense Scaling
- 6.3.20 Motor Stop Options
- 6.3.21 FG Configuration
- 6.3.22 DC Bus Current Limit
- 6.3.23
Protections
- 6.3.23.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
- 6.3.23.2 AVDD Power on Reset (AVDD_POR)
- 6.3.23.3 GVDD Undervoltage Lockout (GVDD_UV)
- 6.3.23.4 BST Undervoltage Lockout (BST_UV)
- 6.3.23.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 6.3.23.6 VSENSE Overcurrent Protection (SEN_OCP)
- 6.3.23.7 Thermal Shutdown (OTSD)
- 6.3.23.8 Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
- 6.3.23.9 Lock Detection Current Limit (LOCK_ILIMIT)
- 6.3.23.10 Motor Lock (MTR_LCK)
- 6.3.23.11 Motor Lock Detection
- 6.3.23.12 MPET Faults
- 6.3.23.13 IPD Faults
- 6.4 Device Functional Modes
- 6.5 External Interface
- 6.6 EEPROM access and I2C interface
- 7 EEPROM (Non-Volatile) Register Map
- 8 RAM (Volatile) Register Map
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RRY|32
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RRY|32
訂購(gòu)信息
Bootstrap Capacitor and GVDD Capacitor Selection
The bootstrap capacitor must be sized to maintain the bootstrap voltage above the undervoltage lockout for normal operation. Equation 13 calculates the maximum allowable voltage drop across the bootstrap capacitor:
ΔVBSTX=12V – 0.85V – 4.45V = 6.7V
where
- VGVDD is the supply voltage of the gate drive
- VBOOTD is the forward voltage drop of the bootstrap diode
- VBSTUV is the threshold of the bootstrap undervoltage lockout
In the example, allowed voltage drop across bootstrap capacitor is 6.7V. TI generally recommends that ripple voltage on both the bootstrap capacitor and GVDD capacitor are minimized as much as possible. Many of commercial, industrial, and automotive applications use ripple value between 0.5V to 1V.
The total charge needed per switching cycle can be estimated with Equation 14:
QTOT=54nC + 115μA/20kHz = 54nC + 5.8nC = 59.8nC
where
- QG is the total MOSFET gate charge
- ILBS_TRAN is the bootstrap pin leakage current
- fSW is the is the PWM frequency
The minimum bootstrap capacitor can then be estimated as below assuming 1V of ΔVBSTx:
CBST_MIN= 59.8nC / 1V = 59.8nF
The calculated value of minimum bootstrap capacitor is 59.8nF. Note that, this value of capacitance is needed at full bias voltage. In practice, the value of the bootstrap capacitor must be greater than calculated value to allow for situations where the power stage can skip pulse due to various transient conditions. TI recommends to use a 100nF bootstrap capacitor in this example. TI recommends to include enough margin and place the bootstrap capacitor as close to the BSTx and SHx pins as possible.
CGVDD= 10*100nF= 1μF
For this example application, choose a 1μF CGVDD capacitor. Choose a capacitor with a voltage rating at least twice the maximum voltage that the capacitor is exposed to because most ceramic capacitors lose significant capacitance when biased. This value also improves the long-term reliability of the system.