SLLSFV1 March 2025 MCF8329A-Q1
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Three Phase BLDC Gate Drivers
- 6.3.2 Gate Drive Architecture
- 6.3.3 AVDD Linear Voltage Regulator
- 6.3.4 Low-Side Current Sense Amplifier
- 6.3.5 Device Interface Modes
- 6.3.6 Motor Control Input Options
- 6.3.7 Bootstrap Capacitor Initial Charging
- 6.3.8 Starting the Motor Under Different Initial Conditions
- 6.3.9 Motor Start Sequence (MSS)
- 6.3.10 Closed Loop Operation
- 6.3.11 Maximum Torque Per Ampere (MTPA) Control
- 6.3.12 Flux Weakening Control
- 6.3.13 Motor Parameters
- 6.3.14 Motor Parameter Extraction Tool (MPET)
- 6.3.15 Anti-Voltage Surge (AVS)
- 6.3.16 Active Braking
- 6.3.17 Output PWM Switching Frequency
- 6.3.18 Dead Time Compensation
- 6.3.19 Voltage Sense Scaling
- 6.3.20 Motor Stop Options
- 6.3.21 FG Configuration
- 6.3.22 DC Bus Current Limit
- 6.3.23
Protections
- 6.3.23.1 PVDD Supply Undervoltage Lockout (PVDD_UV)
- 6.3.23.2 AVDD Power on Reset (AVDD_POR)
- 6.3.23.3 GVDD Undervoltage Lockout (GVDD_UV)
- 6.3.23.4 BST Undervoltage Lockout (BST_UV)
- 6.3.23.5 MOSFET VDS Overcurrent Protection (VDS_OCP)
- 6.3.23.6 VSENSE Overcurrent Protection (SEN_OCP)
- 6.3.23.7 Thermal Shutdown (OTSD)
- 6.3.23.8 Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
- 6.3.23.9 Lock Detection Current Limit (LOCK_ILIMIT)
- 6.3.23.10 Motor Lock (MTR_LCK)
- 6.3.23.11 Motor Lock Detection
- 6.3.23.12 MPET Faults
- 6.3.23.13 IPD Faults
- 6.4 Device Functional Modes
- 6.5 External Interface
- 6.6 EEPROM access and I2C interface
- 7 EEPROM (Non-Volatile) Register Map
- 8 RAM (Volatile) Register Map
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RRY|32
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RRY|32
訂購信息
6.6.2.3 I2C Read Operation
MCF8329A-Q1 read operation over I2C involves the following sequence.
- I2C start condition.
- The sequence starts with I2C target Start Byte.
- The Start Byte is followed by 24-bit Control Word. Bit 23 in the control word has to be 1 as it is a read operation.
- The control word is followed by a repeated start or normal start.
- MCF8329A-Q1 sends the data bytes on SDA. The number of bytes sent by
MCF8329A-Q1 depends on the DLEN field value
in the control word.
- While sending data bytes, the LSB byte is sent first. Refer the examples below for more details.
- 16-bit/32-bit Read – The data from the address mentioned in Control Word is sent back.
- 64-bit Read – 64-bit is treated as two 32-bit read. The address mentioned in Control Word is taken as Addr 0. Addr 1 is calculating internally by MCF8329A-Q1 by incrementing Addr 0 by 2. A total of 8 data bytes are sent by MCF8329A-Q1. The first 4 bytes (sent in LSB first way) are read from Addr 0 and the next 4 bytes are read from Addr 1.
- MCF8329A-Q1 takes some time to process the control word and read data from the given address. This involves some delay. It is quite possible that the repeated start with Target ID will be NACK’d. If the I2C read request has been NACK’d by MCF8329A-Q1, retry after few cycles. During this retry, it is not necessary to send the entire packet along with the control word. It is sufficient to send only the start condition with target ID and read bit.
- If CRC is enabled, then MCF8329A-Q1 sends an additional CRC byte at the end. If CRC is enabled, external MCU I2C controller has to read this additional byte before sending the stop bit. CRC is calculated for the entire packet (Target ID + W bit, Control Word, Target ID + R bit, Data Bytes).
- I2C stop condition.
Figure 6-51 I2C Read Operation Sequence