ZHCSHY8 March 2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Address: 0x2E
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| Reserved | GPIO3_IN | GPIO2_IN | GPIO1_IN | ||||
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7:3 | Reserved | R | 0h | |
| 2 | GPIO3_IN | R | 0h | State of the GPIO3 signal
0h = Logic-low level 1h = Logic high level |
| 1 | GPIO2_IN | R | 0h | State of the GPIO2 signal
0h = Logic-low level 1h = Logic-high level |
| 0 | GPIO1_IN | R | 0h | State of the GPIO1 signal
0h = Logic-low level 1h = Logic-high level |