ZHCSCX2E January 2014 – October 2017 LM15851
PRODUCTION DATA.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DDC_DLY_x | |||||||
| R/W-0xFFh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | DDC_DLY_x | R/W | 0xFFh | DDC delay for configuration preset 0 This register provides fine adjustments to the DDC group delay. The step size is one half of an ADC sample period (t(DEVCLK) / 2). This is equivalent to Equation 17. Equation 17. tO / (2 × D) The legal range for this register is 0 to 2D-1. Illegal values result in undefined behavior.where
Example: When D = 8, the legal register range is 0 to 15. The step size is tO / 16 and the maximum delay is 15 × tO / 16. Programming this register to 0xFF (the default value) powers down and bypasses the fractional delay filter which reduces the DDC latency by 34 ADC sample periods (as compared to the 0 setting). |