PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
The LMK3H0102-Q1 is a 2-output PCIe Gen 1 to Gen 7 compliant reference-less clock generator with Spread Spectrum Clocking (SSC) support. The part is based on TI proprietary Bulk Acoustic Wave (BAW) technology and provides ±25ppm clock outputs without any crystal or external clock reference. The device can provide two SSC clocks, two non-SSC clocks, or one SSC clock and one non-SSC clock at the same time. The device meets the full PCIe compliance from Gen 1 to Gen 7, including Common Clock with or without SSC, Separate Reference No Spread (SRNS), and Separate Reference Independent Spread (SRIS).
The device can be easily configured through either pins or I2C interface. An external DC/DC can be used to power the device. Refer to Power Supply Recommendations for detailed guidelines on power supply filtering and sourcing from DC/DC.
For OTP default settings for each LMK3H0102Txx configuration, refer to the LMK3H0102 Configuration Guide.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | LMK3H0102-Q1 Reference-Less 2-Differential or 5-Single-Ended Output PCIe Gen 1-7 Compliant Programmable BAW Clock Generator datasheet (Rev. B) | PDF | HTML | 24 Oct 2025 |
| Application note | LMK3H0102-Q1 CISPR-25 and CISPR-32 EMI Report | 16 Jun 2025 | ||
| Application note | Clocking Selection Guide for FPD-Link III and FPD-Link IV SerDes | PDF | HTML | 17 Apr 2025 | |
| Technical article | 不只是石英:BAW 時(shí)脈如何重新定義 ADAS 與 IVI | PDF | HTML | 15 Apr 2025 | |
| Technical article | ??? ??? ??: BAW ??? ADAS ? IVI ? ????? ?? | PDF | HTML | 11 Apr 2025 | |
| Technical article | Beyond quartz: How BAW clocks are redefining ADAS and IVI | PDF | HTML | 09 Apr 2025 | |
| Functional safety information | LMK3H0102-Q1 Functional Safety FIT Rate, FMD and Pin FMA | PDF | HTML | 03 Oct 2024 | |
| EVM User's guide | LMK3H0102 Evaluation Module User's Guide | PDF | HTML | 14 Nov 2023 |
For additional terms or required resources, click any title below to view the detail page where available.
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RGT) | 16 | Ultra Librarian |
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PLLatinum Sim User's Guide
PLLatinum Sim software manifest
PLLatinum Sim 1.6.9 includes the ability to manually specify points on a phase noise curve (for VCOs or other devices that do not fit the standard three-point model), and as a result the phase noise estimation for many devices which use a BAW VCO is greatly improved. Also includes a bugfix for cascading noise inputs.