Product details

Function Differential Additive RMS jitter (typ) (fs) 57 Output frequency (max) (MHz) 2000 Number of outputs 4 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 15 Features 2:4 fanout Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
Function Differential Additive RMS jitter (typ) (fs) 57 Output frequency (max) (MHz) 2000 Number of outputs 4 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 15 Features 2:4 fanout Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type LVCMOS, LVDS, LVPECL
VQFN (RGT) 16 9 mm2 3 x 3
  • 2:4 Differential Buffer
  • Selectable Clock Inputs Through Control Terminal
  • Universal Inputs Accept LVPECL, LVDS, and
    LVCMOS/LVTTL
  • Four LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 45 mA
  • Very Low Additive Jitter: <100 fs, RMS in 10-kHz
    to 20-MHz Offset Range:
    • 57 fs, RMS (typical) at 122.88 MHz
    • 48 fs, RMS (typical) at 156.25 MHz
    • 30 fs, RMS (typical) at 312.5 MHz
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum Output Skew: 15 ps
  • LVPECL Reference Voltage, VAC_REF, Available
    for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to +85°C
  • Supports 105°C PCB Temperature (Measured at
    Thermal Pad)
  • ESD Protection Exceeds 2 kV (HBM)
  • 2:4 Differential Buffer
  • Selectable Clock Inputs Through Control Terminal
  • Universal Inputs Accept LVPECL, LVDS, and
    LVCMOS/LVTTL
  • Four LVPECL Outputs
  • Maximum Clock Frequency: 2 GHz
  • Maximum Core Current Consumption: 45 mA
  • Very Low Additive Jitter: <100 fs, RMS in 10-kHz
    to 20-MHz Offset Range:
    • 57 fs, RMS (typical) at 122.88 MHz
    • 48 fs, RMS (typical) at 156.25 MHz
    • 30 fs, RMS (typical) at 312.5 MHz
  • 2.375-V to 3.6-V Device Power Supply
  • Maximum Propagation Delay: 450 ps
  • Maximum Output Skew: 15 ps
  • LVPECL Reference Voltage, VAC_REF, Available
    for Capacitive-Coupled Inputs
  • Industrial Temperature Range: –40°C to +85°C
  • Supports 105°C PCB Temperature (Measured at
    Thermal Pad)
  • ESD Protection Exceeds 2 kV (HBM)

The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. The CDCLVP1204 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1204 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1204 is characterized for operation from –40°C to +85°C.

The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications.

The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. The CDCLVP1204 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.

The CDCLVP1204 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) must be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.

The CDCLVP1204 is characterized for operation from –40°C to +85°C.
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Similar functionality to the compared device
LMK00304 ACTIVE 3.1-GHz differential clock buffer/level translator with 4 configurable outputs Ultra low additive jitter,1:4 Universal Differential Buffer that can support LVPECL

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer datasheet (Rev. F) PDF | HTML 03 Sep 2015
User guide CDCLVP1204 User's Guide 09 Jul 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CDCLVP1204EVM — CDCLVP1204 Evaluation Module

The CDCLVP1204 is a high-performance, low additive phase noise clock buffer. It has two universal input buffers that support either single-ended or differential clock inputs, selectable through a control pin. The device also features on-chip bias generators that can provide the LVPECL common-mode (...)

User guide: PDF
Not available on TI.com
Simulation model

CDCLVP1204RGT HSpice Model

SLAM142.ZIP (116 KB) - HSpice Model
Download
Simulation model

CDCLVPxxxx IBIS Model (Rev. B)

SLLM056B.ZIP (40 KB) - IBIS Model
Download
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Design now
Design tool

PLLATINUMSIM-SW — PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware

Products
Clock buffers
CDCDB2000 — DB2000QL compliant 20-output clock buffer for PCIe® Gen 1 to Gen 5 CDCDB400 — 4-output clock buffer for PCIe® Gen 1 to Gen 6 CDCDB800 — 8-output clock buffer for PCIe® Gen 1 to Gen 6 CDCDB803 — 8-output clock buffer for PCIe® Gen 1 to Gen 6 with selectable SMBus addresses CDCLVC1102 — Low jitter, 1:2 LVCMOS fan-out clock buffer CDCLVC1103 — Low jitter, 1:3 LVCMOS fan-out clock buffer CDCLVC1104 — Low jitter, 1:4 LVCMOS fan-out clock buffer CDCLVC1106 — Low jitter, 1:6 LVCMOS fan-out clock buffer CDCLVC1108 — Low jitter, 1:8 LVCMOS fan-out clock buffer CDCLVC1110 — Low jitter, 1:10 LVCMOS fan-out clock buffer CDCLVC1112 — Low jitter, 1:12 LVCMOS fan-out clock buffer CDCLVC1310 — Universal input, 10-output low impedance LVCMOS buffer CDCLVD110A — 1-to-10 LVDS clock buffer up to 1100-MHz with minimum skew for clock distribution CDCLVD1204 — Low jitter, 2-input selectable 1:4 universal-to-LVDS buffer CDCLVD1208 — Low jitter, 2-input selectable 1:8 universal-to-LVDS buffer CDCLVD1212 — Low jitter, 2-input selectable 1:12 universal-to-LVDS buffer CDCLVD1213 — Low jitter, 1:4 universal-to-LVDS buffer with selectable output divider CDCLVD1216 — Low jitter, 2-input selectable 1:16 universal-to-LVDS buffer CDCLVD2102 — Low jitter, dual 1:2 universal-to-LVDS buffer CDCLVD2104 — Low jitter, dual 1:4 universal-to-LVDS buffer CDCLVD2106 — Low jitter, dual 1:6 universal-to-LVDS buffer CDCLVD2108 — Low jitter, dual 1:8 universal-to-LVDS buffer CDCLVP110 — 1:10 LVPECL/HSTL to LVPECL clock driver CDCLVP1102 — Low jitter 1:2 universal-to-LVPECL buffer CDCLVP111 — 1:10 LVPECL buffer with selectable input CDCLVP111-EP — HiRel, 1:10 LVPECL buffer with selectable input CDCLVP111-SEP — Radiation-tolerant 1:10 LVPECL high-speed clock buffer with selectable input clock driver CDCLVP111-SP — 1:10 high speed clock buffer with selectable input clock driver CDCLVP1204 — Low-jitter, two-input, selectable 1:4 universal-to-LVPECL buffer CDCLVP1208 — Low jitter, 2-input selectable 1:8 universal-to-LVPECL buffer CDCLVP1212 — Low jitter, 2-input selectable 1:12 universal-to-LVPECL buffer CDCLVP1216 — Low jitter, 2-input selectable 1:16 universal-to-LVPECL buffer CDCLVP2102 — Low jitter, dual 1:2 universal-to-LVPECL buffer CDCLVP2104 — Low jitter, dual 1:4 universal-to-LVPECL buffer CDCLVP2106 — Low jitter, dual 1:6 universal-to-LVPECL buffer CDCLVP2108 — Low jitter, dual 1:8 universal-to-LVPECL buffer CDCLVP215 — Dual 1:5 high speed LVPECL fan out buffer LMK00301 — 3-GHz, 10-output differential fanout buffer / level translator LMK00304 — 3.1-GHz differential clock buffer/level translator with 4 configurable outputs LMK00306 — 3.1-GHz differential clock buffer/level translator with 6 configurable outputs LMK00308 — 3.1-GHz differential clock buffer/level translator with 8 configurable outputs LMK00334 — 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator LMK00334-Q1 — Automotive 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator LMK00338 — 8-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator LMK1C1102 — 2-channel output LVCMOS 1.8-V buffer LMK1C1102A — 1.8V,2.5V or 3.3V asynchronous 2 channel output LVCMOS buffer LMK1C1103 — 3-channel output LVCMOS 1.8-V buffer LMK1C1103A — 1.8V,2.5V or 3.3V asynchronous 3 channel output LVCMOS buffer LMK1C1104 — 4-channel output LVCMOS 1.8-V buffer LMK1C1104A — 1.8V,2.5V or 3.3V asynchronous 4 channel output LVCMOS buffer LMK1C1106 — 6-channel output LVCMOS 1.8-V buffer LMK1C1106A — 1.8V,2.5V or 3.3V asynchronous 6 channel output LVCMOS buffer LMK1C1108 — 8-channel output LVCMOS 1.8-V buffer LMK1C1108A — 1.8V,2.5V or 3.3V asynchronous 8 channel output LVCMOS buffer LMK1D1204 — 4-channel output LVDS 1.8-V buffer LMK1D1204P — 4-channel output LVDS 1.8-V, 2.5-V, and 3.3-V?buffer with pin control LMK1D1208 — 8-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer LMK1D1208I — 8-channel output, 1.8-V, 2.5-V, and 3.3-V LVDS buffer with I2C LMK1D1208P — 8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer with pin control LMK1D1212 — 12-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer LMK1D1216 — 16-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer LMK1D2102 — Dual bank 2-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer LMK1D2102L — Low additive jitter LVDS buffer LMK1D2104 — Dual bank 4-channel output 1.8V, 2.5V and 3.3V LVDS buffer LMK1D2104L — Dual bank 4-channel output LVDS 1.8V, 2.5V, and 3.3V buffer with 0.7V output common mode option LMK1D2106 — Dual bank 6-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer LMK1D2106L — Dual bank 2-channel output LVDS 1.8V, 2.5V and 3.3V buffer with 0.7V output common mode option LMK1D2108 — Dual bank 8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer
Clock generators
LMK03318 — Ultra-low jitter clock generator family with single PLL LMK03328 — Ultra-low jitter clock generator family with two independent PLLs LMK3C0105 — 5 output reference-less clock generator with bulk acoustic wave (BAW) LMK3C0105-Q1 — Automotive, 5 output reference-less clock generator with bulk acoustic wave (BAW) LMK3H0102 — Bulk acoustic wave (BAW)-based PCIe Gen 1 to Gen 7-compliant referenceless clock generator LMK3H0102-Q1 — Automotive PCIe gen 7 compliant, reference-less clock generator with bulk acoustic wave (BAW) LMK3H2104 — 4-output, PCIe Gen 1 to Gen 7 compliant, BAW reference-less clock generator, clock mux and buffer LMK3H2108 — 8-output, PCIe Gen 1 to Gen 7 compliant, BAW reference-less clock generator, clock mux and buffer
Clock jitter cleaners
LMK04803 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 1.9-GHz VCO LMK04805 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.2-GHz VCO LMK04806 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.5-GHz VCO LMK04808 — Low-noise clock jitter cleaner with dual loop PLLs and integrated 2.9-GHz VCO LMK04816 — Three input low-noise clock jitter cleaner with dual loop PLLs LMK04821 — Ultra low jitter synthesizer and jitter cleaner with JESD204B support LMK04826 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 1840 to1970-MHz VCO0 LMK04828 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0. LMK04828-EP — Ultra low-noise JESD204B compliant clock jitter cleaner with temperature range -55 to 105c LMK04832 — Ultra-low-noise, 3.2-GHz, 15-output, JESD204B clock jitter cleaner with dual loop LMK04832-SEP — Radiation-tolerant, 30-krad, ultra-low-noise, 3.2-GHz 15-output JESD204C clock jitter cleaner LMK04832-SP — Radiation-hardened-assured (RHA), ultra-low-noise, 3.2-GHz, 15-output clock jitter cleaner
Oscillators
LMK60A0-148351 — 148.352-MHz, LVDS, high-performance, low jitter, differential oscillator LMK60A0-148M — 148.5-MHz, LVDS, high-performance, low jitter, differential oscillator LMK60E0-156257 — 156.257-MHz, LVPECL, ±25 ppm, high-performance, low-jitter oscillator LMK60E0-156M — 156.5-MHz, LVPECL, ±25 ppm, high-performance, low-jitter oscillator LMK60E0-212M — 212.5-MHz, LVPECL, ±25 ppm, high-performance, low-jitter oscillator LMK60E2-100M — 100.0-MHz, LVPECL, ±50 ppm, high-performance, low-jitter oscillator LMK60E2-125M — 125-MHz, LVPECL, ±50 ppm, high-performance, low-jitter oscillator LMK60E2-150M — 150-MHz, LVPECL, ±50 ppm, low jitter, standard oscillator LMK60E2-156M — 156.25-MHz, LVPECL, ±50 ppm, high-performance, low-jitter oscillator LMK60I2-100M — 100-MHz, HCSL, ±50 ppm, high-performance, low-jitter oscillator LMK60I2-322M — 322.27-MHz, HCSL, ±50 ppm, high-performance, low-jitter oscillator LMK61A2-100M — 100-MHz, ±50 ppm, LVDS ultra-low jitter standard differential oscillator LMK61A2-125M — 125-MHz, ±50 ppm, LVDS ultra-low jitter standard differential oscillator LMK61A2-156M — 156.25-MHz, ±50 ppm, LVDS ultra-low jitter standard differential oscillator LMK61A2-312M — 312.5-MHz, ±50 ppm, LVDS ultra-low jitter standard differential oscillator LMK61A2-644M — LVDS ultra-low jitter programmable oscillator with internal EEPROM LMK61E0-050M — 50-MHz, LVPECL ±25 ppm, ultra-low jitter, standard differential oscillator LMK61E0-155M — 155.52-MHz, LVPECL ±25 ppm, ultra-low jitter, standard differential oscillator LMK61E0-156M — 156.25-MHz, ±25 ppm, LVPECL ultra-low jitter standard differential oscillator LMK61E07 — Multi-signal format, ultra-low jitter programmable oscillator with internal EEPROM LMK61E08 — Ultra-low jitter programmable oscillator with internal EEPROM LMK61E0M — LVCMOS ultra-low jitter programmable oscillator with internal EEPROM LMK61E2 — Ultra-low jitter, EEPROM programmable oscillator for medical imaging and test and measurement LMK61E2-100M — 100-MHz, ±50 ppm, LVPECL ultra-low jitter standard differential oscillator LMK61E2-125M — 125-MHz, ±50 ppm, LVPECL ultra-low jitter standard differential oscillator LMK61E2-156M — 156.25-MHz, ±50 ppm, LVPECL ultra-low jitter standard differential oscillator LMK61E2-312M — 312.5-MHz, ±50 ppm, LVPECL ultra-low jitter standard differential oscillator LMK61I2-100M — 100-MHz, ±50 ppm, HCSL ultra-low jitter standard differential oscillator LMK61PD0A2 — ±50 ppm, ultra-low jitter, pin selectable, differential oscillator LMK62A2-100M — 100-MHz, LVDS ±50 ppm, high-performance, low-jitter, standard oscillator LMK62A2-150M — 150-MHz, LVDS ±50 ppm, high-performance, low-jitter, standard oscillator LMK62A2-156M — 156.25-MHz, LVDS ±50 ppm, high-performance, low-jitter oscillator LMK62A2-200M — 200-MHz, LVDS ±50 ppm, high-performance, low-jitter, standard oscillator LMK62A2-266M — 266.66-MHz, LVDS ±50 ppm, high-performance, low-jitter, standard oscillator LMK62E0-156M — 156.25-MHz, LVPECL, ±25 ppm, high-performance, low-jitter oscillator LMK62E2-100M — 100-MHz, LVPECL, ±50 ppm, high-performance, low-jitter oscillator LMK62E2-156M — 156.25-MHz, LVPECL, ±50 ppm, high-performance, low jitter, standard oscillator LMK62I0-100M — 100-MHz, HCSL, ±25 ppm, high-performance, low-jitter oscillator LMK62I0-156M — 156.25-MHz, HCSL, ±25 ppm, high-performance, low-jitter oscillator LMK6C — Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency LVCMOS oscillator LMK6D — Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency LVDS oscillator LMK6H — Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency HCSL oscillator LMK6P — Low-jitter, high-performance, bulk-acoustic-wave (BAW) fixed-frequency LVPECL oscillator
Hardware development
Evaluation board
LMK04832EVM — LMK04832 JESD204B Clock Jitter Cleaner/Clock Generator/Distribution Evaluation Module LMX2571EPEVM — LMX2571-EP evaluation module for 1.34-GHz, low-power, extreme-temperature RF synthesizer LMX2594PSEVM — LMX2594 evaluation module for 15-GHz RF synthesizer with multiple-device phase synchronization XMICR-3P-LMX2492 — LMX2492 X-MWblock evaluation modules XMICR-3P-LMX2572 — LMX2572 X-MWblock evaluation modules XMICR-3P-LMX2592 — LMX2592 X-MWblock evaluation modules XMICR-3P-LMX2594 — LMX2594 X-MWblock evaluation modules XMICR-3P-LMX2595 — LMX2595 X-MWblock evaluation modules
Software
Support software
LMX9830-SW — LMX9830 Application Notes, Software, and Tools LMX9838-SW — LMX9838 Application Notes, Software, and Tools
Download options
Simulation tool

PSPICE-FOR-TI — PSpice? for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Reference designs

TIDA-00352 — SDI Video Aggregation Reference Design

This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is (...)
Test report: PDF
Schematic: PDF
Reference designs

TIDA-00309 — DisplayPort Video 4:1 Aggregation Reference Design

This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a (...)
Test report: PDF
Schematic: PDF
Reference designs

TIDA-00269 — Gigabit Ethernet link aggregator reference design

The Gigabit Ethernet Link Aggregator reference design features the TLK10081 device which is a multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems to reduce the number of physical links by multiplexing lower speed serial links into higher (...)
Test report: PDF
Schematic: PDF
Reference designs

TIDA-00234 — Dual-channel XAUI to SFI reference design for systems with two or more SFP+ optical ports

The TIDA-00234 XAUI to SFI reference design is intended for Enterprise and Service Provider Networking applications like Ethernet Switches and Routers that implement multiple 10G Ethernet compliant Optical (SFP+) ports. This reference design features the TLK10232 device which is the most compact (...)
Test report: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
VQFN (RGT) 16 Ultra Librarian

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E? forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ??????????????

Videos