PLLATINUMSIM-SW — PLLatinum Sim Tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
Very low phase noise floor: –164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
LMK1D1204: 3-mm × 3-mm, 16-pin VQFN (RGT)
LMK1D1208: 5-mm × 5-mm, 28-pin VQFN (RHD)
The LMK1D120x clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 or 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The LMK1D12x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML or LVCMOS.
The LMK1D12x is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage as shown in must be applied to the unused negative input pin.
The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (logic low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature). The LMK1D12x package variant is shown in the table below:
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | LMK1D120x Low Additive Jitter LVDS Buffer datasheet (Rev. B) | PDF | HTML | 14 Jun 2023 |
| Application note | Sine to Square Wave Conversion Using Clock Buffers | PDF | HTML | 03 Sep 2024 | |
| Certificate | LMK1D1208EVM EU Declaration of Conformity (DoC) | 10 Aug 2021 | ||
| EVM User's guide | LMK1D1208 Low-Additive Jitter, Eight LVDS Outputs Clock Buffer Evaluation Board | PDF | HTML | 04 Aug 2021 |
For additional terms or required resources, click any title below to view the detail page where available.
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RHD) | 28 | Ultra Librarian |
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PLLatinum Sim User's Guide
PLLatinum Sim software manifest
PLLatinum Sim 1.6.9 includes the ability to manually specify points on a phase noise curve (for VCOs or other devices that do not fit the standard three-point model), and as a result the phase noise estimation for many devices which use a BAW VCO is greatly improved. Also includes a bugfix for cascading noise inputs.