ZHCSGV5F November 2009 – January 2017 TMS320C6746
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels.
For 3.3 V I/O, Vref = 1.65 V.
For 1.8 V I/O, Vref = 0.9 V.
For 1.2 V I/O, Vref = 0.6 V.
Figure 6-2 Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOLMAX and VOH MIN for output clocks
Figure 6-3 Rise and Fall Transition Time Voltage Reference Levels