ZHCSGV5F November 2009 – January 2017 TMS320C6746
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| NO. | 1.3V, 1.2V | 1.1V | 1.0V | UNIT | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | MIN | MAX | |||||
| 1 | tc(INCLK) | Cycle time, CHn_CLK | SDR mode | 13.33 | 20 | 26.66 | ns | |||
| DDR mode | 26.66 | 40 | 53.33 | |||||||
| 2 | tw(INCLKH) | Pulse width, CHn_CLK high | SDR mode | 5 | 8 | 10 | ns | |||
| DDR mode | 10 | 16 | 20 | |||||||
| 3 | tw(INCLKL) | Pulse width, CHn_CLK low | SDR mode | 5 | 8 | 10 | ns | |||
| DDR mode | 10 | 16 | 20 | |||||||
| 4 | tsu(STV-INCLKH) | Setup time, CHn_START valid before CHn_CLK high | 4 | 5.5 | 6.5 | ns | ||||
| 5 | th(INCLKH-STV) | Hold time, CHn_START valid after CHn_CLK high | 0.8 | 0.8 | 0.8 | ns | ||||
| 6 | tsu(ENV-INCLKH) | Setup time, CHn_ENABLE valid before CHn_CLK high | 4 | 5.5 | 6.5 | ns | ||||
| 7 | th(INCLKH-ENV) | Hold time, CHn_ENABLE valid after CHn_CLK high | 0.8 | 0.8 | 0.8 | ns | ||||
| 8 | tsu(DV-INCLKH) | Setup time,
CHn_DATA/XDATA valid before CHn_CLK high |
4 | 5.5 | 6.5 | ns | ||||
| 9 | th(INCLKH-DV) | Hold time, CHn_DATA/XDATA valid after CHn_CLK high | 0.8 | 0.8 | 0.8 | ns | ||||
| 10 | tsu(DV-INCLKL) | Setup time, CHn_DATA/XDATA valid before CHn_CLK low | 4 | 5.5 | 6.5 | ns | ||||
| 11 | th(INCLKL-DV) | Hold time, CHn_DATA/XDATA valid after CHn_CLK low | 0.8 | 0.8 | 0.8 | ns | ||||
| 19 | tsu(WTV-INCLKL) | Setup time, CHn_WAIT valid before CHn_CLK high | 10 | 12 | 14 | ns | ||||
| 20 | th(INCLKL-WTV) | Hold time, CHn_WAIT valid after CHn_CLK high | 0.8 | 0.8 | 0.8 | ns | ||||
| 21 | tc(2xTXCLK) | Cycle time, 2xTXCLK input clock(1) | 6.66 | 10 | 13.33 | ns | ||||