ZHCSGV5F November 2009 – January 2017 TMS320C6746
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| NO. | 1.3V, 1.2V | 1.1V | 1.0V | UNIT | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | MIN | MAX | |||||
| 1 | tc(SPC)M | Cycle Time, SPI0_CLK, All Master Modes | 20(2) | 256P | 30(2) | 256P | 40(2) | 256P | ns | |
| 2 | tw(SPCH)M | Pulse Width High, SPI0_CLK, All Master Modes | 0.5M-1 | 0.5M-1 | 0.5M-1 | ns | ||||
| 3 | tw(SPCL)M | Pulse Width Low, SPI0_CLK, All Master Modes | 0.5M-1 | 0.5M-1 | 0.5M-1 | ns | ||||
| 4 | td(SIMO_SPC)M | Delay, initial data bit valid on SPI0_SIMO after initial edge on SPI0_CLK(3) | Polarity = 0, Phase = 0,
to SPI0_CLK rising |
5 | 5 | 6 | ns | |||
| Polarity = 0, Phase = 1,
to SPI0_CLK rising |
-0.5M+5 | -0.5M+5 | -0.5M+6 | |||||||
| Polarity = 1, Phase = 0,
to SPI0_CLK falling |
5 | 5 | 6 | |||||||
| Polarity = 1, Phase = 1,
to SPI0_CLK falling |
-0.5M+5 | -0.5M+5 | -0.5M+6 | |||||||
| 5 | td(SPC_SIMO)M | Delay, subsequent bits valid on SPI0_SIMO after transmit edge of SPI0_CLK | Polarity = 0, Phase = 0,
from SPI0_CLK rising |
5 | 5 | 6 | ns | |||
| Polarity = 0, Phase = 1,
from SPI0_CLK falling |
5 | 5 | 6 | |||||||
| Polarity = 1, Phase = 0,
from SPI0_CLK falling |
5 | 5 | 6 | |||||||
| Polarity = 1, Phase = 1,
from SPI0_CLK rising |
5 | 5 | 6 | |||||||
| 6 | toh(SPC_SIMO)M | Output hold time, SPI0_SIMO valid after receive edge of SPI0_CLK | Polarity = 0, Phase = 0,
from SPI0_CLK falling |
0.5M-3 | 0.5M-3 | 0.5M-3 | ns | |||
| Polarity = 0, Phase = 1,
from SPI0_CLK rising |
0.5M-3 | 0.5M-3 | 0.5M-3 | |||||||
| Polarity = 1, Phase = 0,
from SPI0_CLK rising |
0.5M-3 | 0.5M-3 | 0.5M-3 | |||||||
| Polarity = 1, Phase = 1,
from SPI0_CLK falling |
0.5M-3 | 0.5M-3 | 0.5M-3 | |||||||
| 7 | tsu(SOMI_SPC)M | Input Setup Time, SPI0_SOMI valid before receive edge of SPI0_CLK | Polarity = 0, Phase = 0,
to SPI0_CLK falling |
1.5 | 1.5 | 1.5 | ns | |||
| Polarity = 0, Phase = 1,
to SPI0_CLK rising |
1.5 | 1.5 | 1.5 | |||||||
| Polarity = 1, Phase = 0,
to SPI0_CLK rising |
1.5 | 1.5 | 1.5 | |||||||
| Polarity = 1, Phase = 1,
to SPI0_CLK falling |
1.5 | 1.5 | 1.5 | |||||||
| 8 | tih(SPC_SOMI)M | Input Hold Time, SPI0_SOMI valid after receive edge of SPI0_CLK | Polarity = 0, Phase = 0,
from SPI0_CLK falling |
4 | 4 | 5 | ns | |||
| Polarity = 0, Phase = 1,
from SPI0_CLK rising |
4 | 4 | 5 | |||||||
| Polarity = 1, Phase = 0,
from SPI0_CLK rising |
4 | 4 | 5 | |||||||
| Polarity = 1, Phase = 1,
from SPI0_CLK falling |
4 | 4 | 5 | |||||||