ZHCSGV5F November 2009 – January 2017 TMS320C6746
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| NO. | PARAMETER | 1.3V, 1.2V | 1.1V | 1.0V | UNIT | |||||
|---|---|---|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | MIN | MAX | |||||
| 12 | tc(OUTCLK) | Cycle time, CHn_CLK | SDR mode | 13.33 | 20 | 26.66 | ns | |||
| DDR mode | 26.66 | 40 | 53.33 | |||||||
| 13 | tw(OUTCLKH) | Pulse width, CHn_CLK high | SDR mode | 5 | 8 | 10 | ns | |||
| DDR mode | 10 | 16 | 20 | |||||||
| 14 | tw(OUTCLKL) | Pulse width, CHn_CLK low | SDR mode | 5 | 8 | 10 | ns | |||
| DDR mode | 10 | 16 | 20 | |||||||
| 15 | td(OUTCLKH-STV) | Delay time, CHn_START valid after CHn_CLK high | 2 | 11 | 2 | 15 | 2 | 21 | ns | |
| 16 | td(OUTCLKH-ENV) | Delay time, CHn_ENABLE valid after CHn_CLK high | 2 | 11 | 2 | 15 | 2 | 21 | ns | |
| 17 | td(OUTCLKH-DV) | Delay time, CHn_DATA/XDATA valid after CHn_CLK high | 2 | 11 | 2 | 15 | 2 | 21 | ns | |
| 18 | td(OUTCLKL-DV) | Delay time, CHn_DATA/XDATA valid after CHn_CLK low | 2 | 11 | 2 | 15 | 2 | 21 | ns | |
Figure 6-57 uPP Single Data Rate (SDR) Receive Timing
Figure 6-58 uPP Double Data Rate (DDR) Receive Timing
Figure 6-59 uPP Single Data Rate (SDR) Transmit Timing
Figure 6-60 uPP Double Data Rate (DDR) Transmit Timing