ZHCSKL5D November 2019 – March 2022 LMX2694-EP
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| BIASVARAC | 41 | BP | VCO varactor bias. Connect a 10-μF decoupling capacitor to ground. |
| BIASVCO | 3 | BP | VCO bias. Connect a 10-μF decoupling capacitor to ground. Place close to pin. |
| BIASVCO2 | 34 | BP | VCO bias. Connect a 1-μF decoupling capacitor to ground. Place close to pin. |
| CE | 1 | I | Chip Enable. High impedance CMOS input. 1.8-V to 3.3-V logic. Active HIGH powers on the device. |
| CPOUT | 14 | O | Charge pump output. Recommend connecting C1 of loop filter close to this pin. |
| CS# | 28 | I | SPI latch. High impedance CMOS input. 1.8-V to 3.3-V logic. |
| GND | 2, 4, 32, 40, 42, 47 | G | VCO ground. |
| GND | 6, 16, 48 | G | Digital ground. |
| GND | 15 | G | Charge pump ground. |
| GND | 27, 29 | G | Buffer ground. |
| MUXOUT | 23 | O | Multiplexed output. Can output: lock detect, SPI readback and diagnostics. |
| NC | 11, 12, 20, 30, 31, 37, 38, 39 | NC | Pins may be grounded or left unconnected. |
| OSCIN_N | 9 | I | Reference input clock (–). High impedance self-biasing pin. Requires AC-coupling capacitor. (0.1 μF recommended) |
| OSCIN_P | 8 | I | Reference input clock (+). High impedance self-biasing pin. Requires AC-coupling capacitor. (0.1 μF recommended) |
| REFVCO | 44 | BP | VCO supply reference. Connect a 10-μF decoupling capacitor to ground. |
| REFVCO2 | 36 | BP | VCO supply reference. Connect a 10-μF decoupling capacitor to ground. |
| REGIN | 10 | BP | Input reference path regulator decoupling. Connect a 1-μF decoupling capacitor to ground. Place close to pin. |
| REGVCO | 46 | BP | VCO regulator node. Connect a 1-μF decoupling capacitor to ground. |
| RFOUTA_N | 25 | O | Differential output A (–). Requires connecting 50-Ω resistor pullup to VCC as close as possible to pin. |
| RFOUTA_P | 26 | O | Differential output A (+). Requires connecting 50-Ω resistor pullup to VCC as close as possible to pin. |
| RFOUTB_N | 21 | O | Differential output B (–). Requires connecting 50-Ω resistor pullup to VCC as close as possible to pin. |
| RFOUTB_P | 22 | O | Differential output B (+). Requires connecting 50-Ω resistor pullup to VCC as close as possible to pin. |
| SCK | 18 | I | SPI clock. High impedance CMOS input. 1.8-V to 3.3-V logic. |
| SDI | 19 | I | SPI data. High impedance CMOS input. 1.8-V to 3.3-V logic. |
| SYNC | 5 | I | Phase synchronization input. Has programmable threshold. Connect to ground if not being used. |
| SYSREFREQ | 35 | I | SYSREF request input for JESD204B support. Connect to ground if not being used. |
| VCCBUF | 24 | P | Output buffer supply. Connect to 3.3-V and a 0.1-μF decoupling capacitor to ground. |
| VCCCP | 13 | P | Charge pump supply. Connect to 3.3-V and a 0.1-μF decoupling capacitor to ground. |
| VCCDIG | 7 | P | Digital supply. Connect to 3.3-V and a 0.1-μF decoupling capacitor to ground. |
| VCCMASH | 17 | P | Digital supply. Connect to 3.3-V and a 1-μF decoupling capacitor to ground. |
| VCCVCO | 45 | P | VCO supply. Connect to 3.3-V and a 1-μF decoupling capacitor to ground. |
| VCCVCO2 | 33 | P | VCO supply. Connect to 3.3-V and a 1-μF decoupling capacitor to ground. |
| VTUNE | 43 | I | VCO tuning voltage input. Connect a 1.5-nF or more capacitor to VCO ground. See Section 8.1.6 for details. |
| Thermal pad | — | — | Connect the GND pin to the exposed thermal pad for correct operation. Connect the thermal pad to any internal PCB ground plane using multiple vias for good thermal performance. |